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SN74AS869FN

更新时间: 2024-11-19 13:13:47
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SN74AS869FN 数据手册

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SN54AS867, SN54AS869  
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869  
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS  
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995  
SN54AS867, SN54AS869 . . . JT PACKAGE  
Fully Programmable With Synchronous  
SN74ALS867A, SN74ALS869, SN74AS867,  
SN74AS869 . . . DW OR NT PACKAGE  
(TOP VIEW)  
Counting and Loading  
SN74ALS867A and AS867 Have  
Asynchronous Clear; SN74ALS869 and  
AS869 Have Synchronous Clear  
S0  
S1  
A
B
C
D
E
F
G
V
CC  
ENP  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
Fully Independent Clock Circuit  
Q
3
Simplifies Use  
A
Q
B
4
Ripple-Carry Output for n-Bit Cascading  
Q
5
C
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
Q
D
6
Q
7
E
Q
F
8
Q
9
G
H
ENT  
GND  
Q
H
CLK  
10  
11  
12  
description  
RCO  
These synchronous, presettable, 8-bit up/down  
counters feature internal-carry look-ahead  
circuitry for cascading in high-speed counting  
applications. Synchronous operation is provided  
by having all flip-flops clocked simultaneously so  
that the outputs change coincidentally with each  
other when so instructed by the count-enable  
(ENP, ENT) inputs and internal gating. This mode  
of operation eliminates the output counting spikes  
normally associated with asynchronous (ripple-  
clock) counters. A buffered clock (CLK) input  
triggers the eight flip-flops on the rising (positive-  
going) edge of the clock waveform.  
SN54AS867, SN54AS869 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1 28 27 26  
25  
B
C
Q
Q
Q
5
B
C
D
24  
23  
22  
21  
20  
19  
6
D
7
NC  
E
NC  
8
Q
9
E
F
10  
11  
Q
Q
F
These counters are fully programmable; they may  
be preset to any number between 0 and 255. The  
load-input circuitry allows parallel loading of the  
cascaded counters. Because loading is  
synchronous, selecting the load mode disables  
the counter and causes the outputs to agree with  
the data inputs after the next clock pulse.  
G
G
12 13 14 15 16 17 18  
NC – No internal connection  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental  
in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined  
by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO  
thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting  
up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages.  
Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize  
transmission-line effects, thereby simplifying system design.  
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the  
SN74ALS867A and AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q  
outputs until clocking occurs. For the AS867 and AS869, any time ENP and/or ENT is taken high, RCO either  
goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes  
or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely  
by the conditions meeting the stable setup and hold times.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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