Datasheet > SN74AS1821

SN74AS1821

更新时间： 2024-10-01 12:22:31

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
5页	55K
描述
10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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技术参数
数据手册

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SN74AS1821 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	unknown	风险等级：	5.84
系列：	AS	JESD-30 代码：	R-GDIP-T24
长度：	32.004 mm	逻辑集成电路类型：	BUS DRIVER
位数：	10	功能数量：	1
端口数量：	2	端子数量：	24
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	TRUE
封装主体材料：	CERAMIC, GLASS-SEALED	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
传播延迟（tpd）：	10.5 ns	认证状态：	Not Qualified
座面最大高度：	5.08 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	7.62 mm
Base Number Matches：	1

SN74AS1821 数据手册

ꢀꢁ ꢂꢃ ꢄꢀ ꢅꢆ ꢇꢅ

ꢅ ꢈ ꢉꢊꢋ ꢌ ꢊꢍꢀ ꢋꢁ ꢌꢎ ꢏꢐꢄꢑꢎ ꢐ ꢒꢋ ꢓꢉꢐ ꢒ ꢔ ꢓꢀ ꢕ ꢋꢌ ꢖ ꢗ ꢉꢀꢌꢄꢌ ꢎ ꢔ ꢍꢌ ꢓ ꢍꢌꢀ

SDAS131 − APRIL 1987

NT PACKAGE

(TOP VIEW)

• Center V

and GND Configuration Provides

Minimum Lead Inductance in High Current

Switching Applications

10Q

CLK

GND

10D

• Provides Extra Data Width Necessary for Wider

Address/Data Paths or Buses with Parity

• Outputs Have Undershoot Protection Circuitry

• Power-Up High-Impedance State

• Package Options include Plastic DIPS. Use the

’AS821 for Plastic and Ceramic Chip Carriers

and “Small Outline” Package Options.

• Buffered Control inputs to Reduce DC Loading

Effects

description

This 10-bit flip-flop device features three-state

outputs designed specifically for driving highly

capacitive or relatively low-impedance loads. It is

particularly suitable for implementing wider buffer

registers, I/O ports, bidirectional bus drivers with

parity, and working registers. The ten flip-flops are

edge-triggered D-type flip-flops. On the positive

transition of the clock, the Q outputs on the

’AS1821 will be true.

FUNCTION TABLE

(each flip-flop)

OUTPUT

INPUTS

OC CLK

↑

A buffered output-control input can be used to

place the ten outputs in either a normal logic state

(high or low levels) or a high-impedance state. In

the high-impedance state the outputs neither load

†

logic symbol

(7)

nor drive the bus lines significantly.

The

(19)

CLK

high-impedance state and increased drive provide

the capability to drive the bus lines in a

bus-organized system without need for interface

or pull-up components. The output control (OC)

does not affect the internal operation of the

flipflops. Old data can be retained or new data can

be entered while the outputs are in the

high-impedance state.

(8)

(5)

(9)

(4)

(10)

(3)

(11)

(2)

(12)

(1)

(13)

(24)

(14)

(23)

The SN74AS1821 is characterized for operation

from 0°C to 70°C.

(15)

(22)

(16)

(21)

(17)

10D

(20)

10Q

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

ꢓꢏ ꢔ ꢘꢍ ꢑ ꢌꢋ ꢔꢁ ꢘ ꢄꢌꢄ ꢙꢚ ꢛ ꢜꢝ ꢞ ꢟꢠ ꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ ꢓꢝ ꢜꢨꢣ ꢢꢠ ꢡ

ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠ ꢙꢜ ꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢌꢤꢫ ꢟ ꢡ ꢋꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚ ꢨꢟꢝ ꢨ

ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢓꢝ ꢜ ꢨꢣꢢ ꢠ ꢙ ꢜꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡꢡ ꢙꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠ ꢙꢚꢮ ꢜꢛ ꢟꢧ ꢧ

ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5

中文翻译

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与SN74AS1821相关器件

型号	品牌	获取价格	描述	数据表
SN74AS182FN-00	TI	获取价格	AS SERIES, 4-BIT LOOK-AHEAD CARRY GENERATOR, PQCC20
SN74AS1832	TI	获取价格	HEX 2-INPUT OR DRIVER
SN74AS1832D	TI	获取价格	AS SERIES, HEX 2-INPUT OR GATE, PDSO20, PLASTIC, SO-20
SN74AS1832DR	TI	获取价格	AS SERIES, HEX 2-INPUT OR GATE, PDSO20, PLASTIC, SO-20
SN74AS1832DWR	TI	获取价格	AS SERIES, HEX 2-INPUT OR GATE, PDSO20
SN74AS1832N	ROCHESTER	获取价格	AS SERIES, HEX 2-INPUT OR GATE, PDIP20, 0.300 INCH, PLASTIC, DIP-20
SN74AS1832N	TI	获取价格	AS SERIES, HEX 2-INPUT OR GATE, PDIP20, 0.300 INCH, PLASTIC, DIP-20
SN74AS1832NP3	TI	获取价格	SN74AS1832NP3
SN74AS1843	TI	获取价格	9-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AS1843NT	TI	获取价格	9-Bit Bus Interface D-Type Latches With 3-State Outputs 24-PDIP 0 to 70

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