SN74ALS74AN

更新时间： 2024-01-17 15:43:28

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
7页	116K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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数据手册
替代型号

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SN74ALS74AN 数据手册

SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS143C – APRIL 1982 – REVISED AUGUST 1995

SN54ALS74A, SN54AS74A . . . J PACKAGE

SN74ALS74A, SN74AS74A . . . D OR N PACKAGE

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

(TOP VIEW)

1CLR

1CLK

1PRE

2CLR

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

2CLK

2PRE

(C = 50 pF)

(MHz)

′ALS74A

′AS74A

GND

134

description

SN54ALS74A, SN54AS74A . . . FK PACKAGE

(TOP VIEW)

These devices contain two independent

positive-edge-triggered D-type flip-flops. A low

level at the preset (PRE) or clear (CLR) inputs sets

or resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the data (D) input meeting the

setup-time requirements are transferred to the

outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a voltage

level and is not directly related to the rise time of

CLK. Following the hold-time interval, data at the

D input can be changed without affecting the

levels at the outputs.

20 19

1CLK

17 NC

1PRE

2CLK

2PRE

9 10 11 12 13

NC – No internal connection

The SN54ALS74A and SN54AS74A are

characterized for operation over the full military

temperature range of –55°C to 125°C. The

SN74ALS74AandSN74AS74Aarecharacterized

for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

†

The output levels in this configuration are not

specifiedtomeettheminimumlevelsforV ifthe

lows at PRE and CLR are near V maximum.

Furthermore, this configuration is nonstable; that

is, it does not persist when PRE or CLR returns to

its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

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SN74ALS74AN 替代型号

型号	品牌	替代类型	描述	数据表
SN74ALS74ANE4	TI	类似代替	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
DM74ALS74AN	FAIRCHILD	功能相似	Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
74ALS74AN	NXP	功能相似	Dual D-type flip-flop with set and reset

与SN74ALS74AN相关器件

型号	品牌	获取价格	描述	数据表
SN74ALS74AN1	TI	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,DIP,14PIN,PLASTIC
SN74ALS74AN3	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS74ANE4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS74ANP3	TI	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,DIP,14PIN,PLASTIC
SN74ALS74ANS	TI	获取价格	ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTI
SN74ALS74ANSE4	TI	获取价格	IC ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLA
SN74ALS74ANSR	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS74ANSRE4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS74ANSRG4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ALS74FN	TI	获取价格	IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,LDCC,20PIN,PLASTIC

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