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SN54LS395J PDF预览

SN54LS395J

更新时间: 2024-09-27 13:13:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器输出元件
页数 文件大小 规格书
6页 199K
描述
Parallel In Parallel Out, LS Series, 4-Bit, Right Direction, True Output, TTL, CDIP16, CERAMIC, DIP-16

SN54LS395J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.51
其他特性:TOTEMPOLE SERIAL SHIFT RIGHT OUTPUT计数方向:RIGHT
系列:LSJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.495 mm
逻辑集成电路类型:PARALLEL IN PARALLEL OUT位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:45 MHzBase Number Matches:1

SN54LS395J 数据手册

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SN74LS395  
4-BIT SHIFT REGISTER  
WITH 3-STATE OUTPUTS  
The SN74LS395 is a 4-Bit Register with 3-state outputs and can operate  
in either a synchronous parallel load or a serial shift-right mode, as  
determined by the Select input. An asynchronous active LOW Master Reset  
(MR) input overrides the synchronous operations and clears the register. An  
active HIGH Output Enable (OE) input controls the 3-state output buffers, but  
does not interfere with the other operations. The fourth stage also has a  
conventional output for linking purposes in multi-stage serial operations.  
4-BIT SHIFT REGISTER  
WITH 3-STATE OUTPUTS  
LOW POWER SCHOTTKY  
Shift Left or Parallel 4-Bit Register  
3-State Outputs  
Input Clamp Diodes Limit High-Speed Termination Effects  
J SUFFIX  
CERAMIC  
CASE 620-09  
CONNECTION DIAGRAM DIP (TOP VIEW)  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
ORDERING INFORMATION  
P P  
0
Parallel Inputs  
Serial Data Input  
Mode Select Input  
Clock (Active LOW) Input  
Master Reset (Active LOW) Input  
Output Enable (Active HIGH) Input  
3-State Register Outputs  
Register Output  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
65 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
15 U.L.  
3
D
SN74LSXXXJ  
Ceramic  
S
S
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
CP  
MR  
OE  
O O  
0
3
3
5 U.L.  
Q
LOGIC SYMBOL  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
FAST AND LS TTL DATA  
5-551  

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