SN54AS109A

更新时间： 2024-09-29 22:59:15

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
9页	137K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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SN54AS109A 数据手册

SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDAS198B – APRIL 1982 – REVISED AUGUST 1995

SN54ALS109A, SN54AS109A . . . J PACKAGE

SN74ALS109A, SN74AS109A . . . D OR N PACKAGE

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

(TOP VIEW)

1CLR

2CLR

TYPICAL MAXIMUM TYPICAL POWER

CLOCK

FREQUENCY

(MHz)

DISSIPATION

PER FLIP-FLOP

(mW)

TYPE

1CLK

1PRE

2CLK

′ALS109A

′AS109A

11 2PRE

129

GND

description

These devices contain two independent J-K

positive-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the J and K inputs meeting the

setup-time requirements are transferred to the

outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a voltage

level and is not directly related to the rise time of

the clock pulse. Following the hold-time interval,

data at the J and K inputs can be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by

grounding K and tying J high. They also can

perform as D-type flip-flops if J and K are tied

together.

SN54ALS109A, SN54AS109A . . . FK PACKAGE

(TOP VIEW)

1 20 19

1CLK

1PRE

2CLK

2PRE

9 10 11 12 13

NC – No internal connection

The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range

of –55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

Toggle

↑

†

The output levels in this configuration are not specified to

meet the minimum levels for V if the lows at PRE and

maximum. Furthermore, this

CLR are near

configuration is nonstable; that is, it does not persist when

either PRE or CLR returns to its inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN54AS109A相关器件

型号	品牌	获取价格	描述	数据表
SN54AS109AFK	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54AS109AJ	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54AS109FH	TI	获取价格	J-Kbar Flip-Flop
SN54AS109J	TI	获取价格	Dual J-K Positive-Edge-Triggered Flip-Flops 16-CDIP -55 to 125
SN54AS10FH	TI	获取价格	IC,LOGIC GATE,3 3-INPUT NAND,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS10FK	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATES
SN54AS10J	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATES
SN54AS10J-00	TI	获取价格	AS SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14
SN54AS11	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN54AS112FH-00	TI	获取价格	AS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20

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