5秒后页面跳转
SN54AS10J-00 PDF预览

SN54AS10J-00

更新时间: 2024-09-30 20:39:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
19页 858K
描述
AS SERIES, TRIPLE 3-INPUT NAND GATE, CDIP14

SN54AS10J-00 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44系列:AS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):13 mA
传播延迟(tpd):5 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54AS10J-00 数据手册

 浏览型号SN54AS10J-00的Datasheet PDF文件第2页浏览型号SN54AS10J-00的Datasheet PDF文件第3页浏览型号SN54AS10J-00的Datasheet PDF文件第4页浏览型号SN54AS10J-00的Datasheet PDF文件第5页浏览型号SN54AS10J-00的Datasheet PDF文件第6页浏览型号SN54AS10J-00的Datasheet PDF文件第7页 
ꢋ ꢌꢍꢎ ꢅꢏ ꢉꢐ ꢑꢍ ꢁꢎꢒꢋ ꢉ ꢎꢓ ꢀꢍꢋ ꢍ ꢔꢏꢑ ꢁꢄꢁ ꢕꢉ ꢖ ꢄꢋꢏ  
SDAS002B − MARCH 1984 − REVISED DECEMBER 1994  
SN54ALS10A, SN54AS10 . . . J PACKAGE  
SN74ALS10A, SN74AS10 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3C  
3B  
3A  
3Y  
description  
These devices contain three independent 3-input  
positive-NAND gates. They perform the Boolean  
functions Y = A B C or Y = A + B + C in positive  
logic.  
2Y  
GND  
8
The SN54ALS10A and SN54AS10 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS10A and SN74AS10 are characterized  
for operation from 0°C to 70°C.  
SN54ALS10A, SN54AS10 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
FUNCTION TABLE  
(each gate)  
2A  
NC  
2B  
4
5
6
7
8
1Y  
NC  
3C  
NC  
3B  
17  
16  
15  
14  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
NC  
2C  
L
H
H
H
9 10 11 12 13  
X
X
X
NC − No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
1A  
&
2
2
12  
12  
6
1B  
1C  
1Y  
2Y  
3Y  
1B  
1Y  
2Y  
3Y  
13  
13  
1C  
3
3
4
5
2A  
4
2A  
6
2B  
5
2B  
2C  
2C  
9
3A  
9
10  
8
3A  
3B  
3C  
3B  
10  
11  
8
11  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
ꢋꢣ  
Copyright 1994, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

与SN54AS10J-00相关器件

型号 品牌 获取价格 描述 数据表
SN54AS11 TI

获取价格

TRIPLE 3-INPUT POSITIVE-AND GATES
SN54AS112FH-00 TI

获取价格

AS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
SN54AS112J-00 TI

获取价格

AS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
SN54AS113FH TI

获取价格

IC,FLIP-FLOP,DUAL,J/K TYPE,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS113J TI

获取价格

IC,FLIP-FLOP,DUAL,J/K TYPE,AS-TTL,DIP,14PIN,CERAMIC
SN54AS113J-00 TI

获取价格

AS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN54AS114FH TI

获取价格

IC,FLIP-FLOP,DUAL,J/K TYPE,AS-TTL,LLCC,20PIN,CERAMIC
SN54AS114FH-00 TI

获取价格

AS SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
SN54AS114J-00 TI

获取价格

AS SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN54AS1181FK TI

获取价格

AS SERIES, 4-BIT ARITHMETIC LOGIC UNIT, CQCC28