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SN54ABTH162260WD

更新时间： 2024-09-23 23:06:07
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德州仪器 - TI 锁存器电阻器输出元件
页数 文件大小 规格书
8页 140K
描述
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS

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SN54ABTH162260WD 数据手册

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SN54ABTH162260, SN74ABTH162260  
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES  
WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS  
SCBS240D – JUNE 1992 – REVISED MAY 1997  
SN54ABTH162260 . . . WD PACKAGE  
SN74ABTH162260 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
B-Port Outputs Have Equivalent 25-Ω  
Series Resistors, So No External Resistors  
Are Required  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEA  
LE1B  
2B3  
GND  
2B2  
OE2B  
LEA2B  
2B4  
GND  
2B5  
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
3
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
2B1  
2B6  
7
V
V
CC  
CC  
8
A1  
A2  
A3  
GND  
A4  
A5  
A6  
A7  
A8  
2B7  
2B8  
2B9  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
GND  
2B10  
2B11  
2B12  
1B12  
1B11  
1B10  
GND  
1B9  
= 5 V, T = 25°C  
A
High-Impedance State During Power Up  
and Power Down  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
A9  
GND  
A10  
A11  
A12  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1B8  
1B7  
V
V
CC  
CC  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center  
Spacings  
1B1  
1B2  
GND  
1B3  
LE2B  
SEL  
1B6  
1B5  
GND  
1B4  
LEA1B  
OE1B  
description  
The ’ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data  
paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include  
multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface  
applications. These devices are also useful in memory-interleaving applications.  
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are available for address and/or data transfer. The  
output-enable (OE1B, OE2B, and OEA) inputs control the bus-transceiver functions. The OE1B and OE2B  
control signals also allow bank control in the A-to-B direction.  
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,  
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the  
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains  
latched until the latch-enable input is returned high.  
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce  
overshoot and undershoot.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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