Datasheet > SMM150ER01

SMM150ER01

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
SUMMIT		监视器
页数	文件大小	规格书
22页	383K
描述
Single-Channel Supply Voltage Marginer/Monitor

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数据手册

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SMM150ER01 数据手册

SMM150

Preliminary Information

INTERNAL BLOCK DIAGRAM

FAULT#

READY

VDD

VREF =

COMP1

1.25V or 0.5V

OV/UV

VDD_CAP

GND

VREF

V_REF

Glitch

Filter

Output

Control

COMP2

TRIM

50kΩ

Up/Dn

MUP

MDN

Digital

Margin

Control

8-bit DAC

Comparator

Target

Logic

Halt

SW1

50kΩ

Clock

MUX

10Bit

ADC

I²C

SCL

SDA

Interface

SW2

Configuration

Registers

& Memory

CAPM

Figure 2 – SMM150 Controller Internal Block Diagram.

PACKAGE AND PIN CONFIGURATION

28 Pad QFN

20 Ball Ultra CSP^TM

Top View

Bottom View

Pin 1

SCL

MDN VDD_CAP VDD

Pin 1

SDA

TRIM

COMP1

28 27 26 25 24

SCL

VDD

TRIM

COMP1

READY

GND

MUP

SMM150

FAULT#

READY

GND

CAP_M

10 11

COMP2

Summit Microelectronics, Inc

2075 2.6 05/13/05

1 234 5 6 7...22

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