ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢅꢇ
ꢈ ꢉꢇꢊꢋ ꢌꢍꢀ ꢀꢎ ꢀꢏ ꢐꢁ ꢊꢉꢑ ꢍ ꢐꢀ ꢀ ꢑ ꢉ
SGUS011D − APRIL 1991 − REVISED SEPTEMBER 2004
D
D
D
D
D
Class B High-Reliability Processing
D
D
Flexible Multi-Processor Interface
Packaging Options
− 145-Pin Grid Array Ceramic Package
(GB Suffix)
− 132-Pin Ceramic Quad Flat Pack
(Unformed Lead) (HT Suffix)
1-µm CMOS Technology
Military Operating Temperature Range
−55°C to 125°C
SMJ34020A-32/40
125/100-ns Instruction Cycle Time
145-PIN GRID ARRAY PACKAGE
(TOP VIEW)
Fully Programmable 32-Bit
General-Purpose Processor With
512-Megabyte Linear Address Range
(Bit Addressable)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
D
Second-Generation Graphics System
Processor
− Object-Code Compatible With the
SMJ34010
− Enhanced Instruction Set
− Optimized Graphics Instructions
− Coprocessor Interface
B
C
D
E
F
G
H
J
K
L
M
N
P
R
D
D
Pixel Processing, XY Addressing, and
Window Checking Built Into the Instruction
Set
Programmable 1-, 2-, 4-, 8-, 16-, or 32-Bit
Pixel Size With 16 Boolean and Six
Arithmetic Pixel Processing Options
(Raster Ops)
D
D
512-Byte LRU On-Chip Instruction Cache
132-PIN QUAD FLATPACK
(TOP VIEW)
Optimized DRAM/VRAM Interface
− Page-Mode for Burst Memory Operations
− Dynamic Bus Sizing (16-Bit and
32-Bit Transfers)
− Byte-Oriented CAS Strobes
D
Flexible Host Processor Interface
− Supports Host Transfers
− Direct Access to All of the SMJ34020A
Address Space
1
99
− Implicit Addressing
− Prefetch for Enhanced Read Access
D
D
Programmable CRT Control
− Composite Sync Mode
− Separate Sync Mode
− Synchronization to External Sync
33
67
Direct Support for Special Features of
1M VRAMs
− Load Write Mask
− Load Color Mask
− Block Write
− Write Using the Write Mask
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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