SMH4811A
Preliminary
PIN DESCRIPTIONS
DRAIN SENSE (1)
OV (10)
TheDRAINSENSEinputmonitorsthevoltageatthedrain The OV pin is used as an over-voltage supply monitor,
oftheexternalpowerMOSFETswitchwithrespecttoVSS
.
typically in conjunction with an external resistor ladder.
An internal 10µA source pulls the DRAIN SENSE signal VGATE will be disabled if OV is greater than 2.5V. A filter
towards the 5V reference level. DRAIN SENSE must be delay is available on the OV input.
held below 2.5V to enable the PG outputs.
5.0VREF & 2.5VREF (11 & 12)
These are precision 5V and 2.5V output reference volt-
VGATE (2)
The VGATE output activates an external power MOSFET ages that may be use to expand the logic input functions
switch. This signal supplies a constant current output on the SMH4803A. The reference outputs are with re-
(100µA typical), which allows easy adjustment of the spect to VSS
.
MOSFET turn on slew rate.
ENPG (14)
EN/TS (3)
This is an active high input that controls the PG# output.
The Enable/Temperature Sense input is the master en- When ENPG is pulled low the PG# output is immediately
able input. If EN/TS is less than 2.5V, VGATE will be placed in a high impedance state. This pin has an internal
disabled. This pin has an internal 200kΩ pull-up to 5V. 50kΩ pull-up to 5V.
PD1# and PD2# (4 & 5)
PG# (15)
These are logic level active low inputs that can optionally The PG# pin is an open-drain, active-low output with no
be employed to enable VGATE and the PG outputs when internal pull-up resistor. It can be used to switch a load or
they are at VSS. These pins each have an internal 50kΩ enable a DC/DC converter. PG# is enabled immediately
pull-up to 5V.
after VGATE reaches VDD – VGT and the DRAIN SENSE
voltage is less than 2.5V. Voltage on these pins cannot
exceed 12V, as referenced to VSS.
FAULT# (6)
This is an open-drain, active-low output that indicates the
VDD (16)
fault status of the device.
VDD is the positive supply connection. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the VDD pin to limit the regulator current (RD in
the application illustrations).
CBSENSE (7)
The circuit breaker sense input is used to detect over-
current conditions across an external, low value sense
resistor (RS) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than tCBD will trip the circuit breaker. A program-
mable Quick-Trip™ sense point is also available.
VSS (8)
VSS is connected to the negative side of the supply.
UV (9)
The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program-
mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.
RECOMMENDED OPERATING CONDITIONS
Temperature
–40°C to 85°C.
2044 6.6 03/27/09
3
SUMMIT MICROELECTRONICS, Inc.
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