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SMH4803AEL PDF预览

SMH4803AEL

更新时间: 2024-01-16 22:40:52
品牌 Logo 应用领域
SUMMIT 控制器
页数 文件大小 规格书
22页 177K
描述
Distributed Power Hot-Swap Controller

SMH4803AEL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.92湿度敏感等级:1
Base Number Matches:1

SMH4803AEL 数据手册

 浏览型号SMH4803AEL的Datasheet PDF文件第6页浏览型号SMH4803AEL的Datasheet PDF文件第7页浏览型号SMH4803AEL的Datasheet PDF文件第8页浏览型号SMH4803AEL的Datasheet PDF文件第10页浏览型号SMH4803AEL的Datasheet PDF文件第11页浏览型号SMH4803AEL的Datasheet PDF文件第12页 
SMH4803  
ENPGA (16)  
test all combinations (all 128 possibilities) are readily  
The ENPGA input controls the PG2# and PG3# outputs. available as off the shelf stock items.  
When ENPGA is pulled low, the PG2# output is immedi-  
atelyplacedinahighimpedancestate.IfENPGAisdriven  
high, thenthePG2#outputwillimmediatelybedrivenlow,  
Power Good Delay  
The PG delay timer that controls the delay from PG1# to  
PG2# and PG2# to PG3# being asserted can be set to  
typical values of 5ms, 20ms, 80ms or 160ms.  
provided PG1# has been active for at least tPGD  
.
PG3# (17)  
Quick-Trip Circuit Breaker Threshold  
The Quick-Trip circuit breaker threshold can be set to  
200mV, 100mV, 60mv or OFF. This is the threshold  
voltage drop across RS that is placed between VSS and  
CBSense.  
PG3# is an open drain active low output with no internal  
pull-up. PG3# is the last power good signal to be enabled  
after Vgate, PG1# and PG2# have been turned on. PG3#  
is delayed PGD after PG2# is active and 2xPGD after  
PG1# is active. PG3# can be used to switch a third load  
or a DC/DC converter.  
Circuit Breaker Delay  
The circuit breaker delay defines the period of time the  
voltagedropacrossRS isgreaterthan50mVbutlessthan  
VQCB before the Vgate output will be shut down. This is  
effectivelyafiltertopreventspuriousshutdownsofVgate.  
Thedelaysthatcanbeprogrammedare5µs, 50µs, 150µs  
and 400µs.  
PG1# (18)  
PG1# is an open drain active low output with no internal  
pull-up. PG1# is enabled after Vgate is enabled and  
voltage across the load is within spec. PG1# can be used  
to switch a load or enable a DC/DC converter.  
PG2# (19)  
Pin Detect  
PG2# is an open drain active low output with no internal  
pull-up.PG2#isenabledafterVgateandPG1#havebeen  
turned on. PG2# is delayed PGD after PG1# is active.  
PG2# can be used to switch a second load or a DC/DC  
converter.  
The Pin Detect function can be enabled or disabled.  
VDD (20)  
VDD is the positive supply connection. An internal shunt  
regulator connected between VDD and VSS develops  
approximately 12 volts that supplies the SMH4803. A  
resistor must be placed in series with the VDD pin to limit  
the regulator current (RD in the application illustrations).  
PROGRAMMABLE FEATURES  
Because the SMH4803 is electrically programmable it  
can be fine-tuned for a wide variety of applications prior to  
shipmenttothecustomer.Becauseofthisamanufacturer  
can use a common part type across a wide range of  
boards that are used on a common host but have different  
electrical loads, power-on timing requirements, host volt-  
age monitoring needs etc.  
This ability to use a common solution across many plat-  
forms shifts the focus of design away from designing a  
new power interface for each board to concentrating on  
the value added back-end logic.  
Because the programming of the features is done at final  
SUMMIT MICROELECTRONICS  
2041 8.4 6/15/00  
9

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