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SM840001KA PDF预览

SM840001KA

更新时间: 2024-01-11 02:27:55
品牌 Logo 应用领域
麦瑞 - MICREL 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
8页 308K
描述
106.25MHz Ultra-Low Jitter Clock Synthesizer

SM840001KA 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
其他特性:IT ALSO OPERATES WITH 3.3VJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:4.4 mm
湿度敏感等级:1端子数量:8
最高工作温度:75 °C最低工作温度:-40 °C
最大输出时钟频率:226.66 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:26.5625 MHz认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

SM840001KA 数据手册

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Micrel, Inc.  
SM840001  
Functional Description  
The SM840001 provides a high performance and high  
accuracy solution for a precision clock source at 106.25  
or 212.50MHz derived from a low cost 26.5625MHz Xtal.  
A single 12mA LVCMOS output is provided with tri state  
capability, controlled via an external pin (OE).  
ratios. Output Divider ratios are fixed at either ÷15 or ÷30  
controlled via the FSEL pin, and the feedback divider  
also fixed at ÷120. Duty Cycle is inherently improved and  
guarantees tight control and stability on this critical  
specification. The provides improved specifications for  
Duty Cycle, Jitter, Phase Noise, Power Consumption,  
and noise sensitivity. Additionally, the SM840001 will  
operate at either 3.3V or 2.5V supplies.  
The design of the SM840001 consumes very low power  
in the PLL due to a patented technology in the VCO and  
the associated dividers. The VCO range is ~3.2GHz to  
3.5GHz providing high resolution and easy integer divide  
Switching Waveforms  
RMS Phase Noise/Jitter  
Phase Noise Plot: 212.5MHz @ 3.3V  
Phase Noise Plot: 106.25MHz @ 3.3V  
M9999-031810-B  
hbwhelp@micrel.com or (408) 955-1690  
March 2010  
5

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