Datasheet > SM34020AGBS40

SM34020AGBS40

更新时间： 2025-07-15 12:21:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
94页	1634K
描述
GRAPHICS SYSTEM PROCESSOR

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技术参数
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SM34020AGBS40 技术参数

生命周期：	Not Recommended	零件包装代码：	PGA
包装说明：	PGA, PGA145,15X15	针数：	145
Reach Compliance Code：	not_compliant	HTS代码：	8542.31.00.01
Factory Lead Time：	6 weeks	风险等级：	5.66
最大时钟频率：	40 MHz	外部数据总线宽度：	32
JESD-30 代码：	S-CPGA-P145	每像素最大位数：	32
端子数量：	145	最高工作温度：	110 °C
最低工作温度：	-40 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	PGA	封装等效代码：	PGA145,15X15
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	子类别：	Graphics Processors
最大压摆率：	280 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	PIN/PEG
端子节距：	2.54 mm	端子位置：	PERPENDICULAR
处于峰值回流温度下的最长时间：	NOT SPECIFIED	uPs/uCs/外围集成电路类型：	GRAPHICS PROCESSOR
Base Number Matches：	1

SM34020AGBS40 数据手册

Not Recommended for New Designs

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ꢇ ꢈꢆꢉꢊ ꢋꢌꢀ ꢀꢍ ꢀꢎ ꢏꢁ ꢉꢈꢐ ꢌ ꢏꢀ ꢀ ꢐ ꢈ

SGUS057 − FEBRUARY 2005

Terminal Functions (Continued)

TERMINAL

NAME TYPE

DESCRIPTION

†

VIDEO INTERFACE (CONTINUED)

HSYNC

I/O

Horizontal sync. HSYNC is the horizontal sync signal that controls external video circuitry. HSYNC can be

programmed to be either an input or an output by modifying a control bit in the DPYCTL register.

As an output, HSYNC is the active-low horizontal-sync signal generated by the SM34020A on-chip video

timers.

As an input, HSYNC synchronizes the SM34020A video-control registers to externally generated

horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this

allows for any external pipelining of signals.

Immediately following reset, HSYNC is configured as an input.

SCLK

Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the SM34020A

to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload cycles. (SCLK can

be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency).

VCLK

Video clock. VCLK is derived from a multiple of the video system’s dot clock and is used internally to drive the video

timing logic.

VSYNC

I/O

Vertical sync. VSYNC is the vertical sync signal that controls external video circuitry. VSYNC can be programmed

to be either an input or an output by modifying a control bit in the DPYCTL register.

As an output, VSYNC is the active-low vertical-sync signal generated by the SM34020A on-chip video timers.

As an input, VSYNC synchronizes the SM34020A video-control registers to externally generated

vertical-sync pulses. The actual synchronization can be programmed to begin at any horizontal line; this

allows for any external pipelining of signals.

Immediately following reset, VSYNC is configured as an input.

†

‡

I = input, O = output

For proper SM34020A operation, all V

and V pins must be connected externally.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

1...4 5 678 9 10...94

中文翻译

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SM34020AGBS40 替代型号

型号	品牌	替代类型	描述	数据表
SM34020AGBM40	TI	类似代替	GRAPHICS SYSTEM PROCESSOR
SMJ34020AGBM40	TI	功能相似	GRAPHICS SYSTEM PROCESSOR

与SM34020AGBS40相关器件

型号	品牌	获取价格	描述	数据表
SM34020AHTM32	TI	获取价格	GRAPHICS SYSTEM PROCESSOR
SM34020AHTM40	TI	获取价格	GRAPHICS SYSTEM PROCESSOR
SM34020APCM40	TI	获取价格	GRAPHICS SYSTEM PROCESSOR
SM34020APCML40	TI	获取价格	GRAPHICS PROCESSOR, PQFP144, PLASTIC, QFP-144
SM3404T-10	CYPRESS	获取价格	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50,
SM3404T-6.0I	CYPRESS	获取价格	Synchronous DRAM, 1MX16, 4.5ns, CMOS, PDSO50,
SM3404T-7.5I	CYPRESS	获取价格	Synchronous DRAM, 1MX16, 4.6ns, CMOS, PDSO50,
SM34061GB	ETC	获取价格	Non-VGA Video Controller
SM340A	UNIOHM	获取价格	3.0 AMP SURFACE MOUNT SCHOTTKY BARRIER RECTIFIERS
SM340A	SECOS	获取价格	Voltage 20V ~ 100V 3.0 Amp Surface Mount Schottky Barrier Rectifiers

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