Datasheet > SM320VC33-EP

SM320VC33-EP

更新时间： 2024-10-02 11:58:19

品牌	Logo	应用领域
德州仪器 - TI		数字信号处理器
页数	文件大小	规格书
62页	997K
描述
DIGITAL SIGNAL PROCESSOR

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SM320VC33-EP 数据手册

SM320VC33-EP

DIGITAL SIGNAL PROCESSOR

SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003

Controlled Baseline

-- One Assembly/Test Site, One Fabrication

Site

Boot-Program Loader

EDGEMODE Selectable External Interrupts

32-Bit Instruction Word, 24-Bit Addresses

Eight Extended-Precision Registers

Extended Temperature Performance of

-- 4 0 °C to 100°C (A Suffix), and

-- 5 5 °C to 125°C (M Suffix)

Fabricated Using the 0.18-μm (l_eff-Effective

Gate Length) TImeline™ Technology by

Texas Instruments (TI)

Enhanced Diminishing Manufacturing

Sources (DMS) Support

On-Chip Memory-Mapped Peripherals:

-- O n e S e r i a l P o r t

-- Tw o 3 2 - B i t T i m e r s

-- Direct Memory Access (DMA)

Coprocessor for Concurrent I/O and CPU

Operation

Enhanced Product Change Notification

Qualification Pedigree^†

High-Performance Floating-Point Digital

Signal Processor (DSP):

-- SM320VC33-120EP (PGE Suffix)

-- 17-ns Instruction Cycle Time

-- 120 Million Floating-Point Operations

Per Second (MFLOPS)

-- 60 Million Instructions Per Second

(MIPS)

-- SM320VC33-150EP (GNM Suffix)

-- 13-ns Instruction Cycle Time

-- 150 Million Floating-Point Operations

Per Second (MFLOPS)

144-Pin Low-Profile Quad Flatpack (LQFP)

(PGE Suffix) and 144-Pin Non-hermetic

Ceramic Ball Grid Array (CBGA)

(GNM Suffix)

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Two Low-Power Modes

-- 75 Million Instructions Per Second

(MIPS)

Two- and Three-Operand Instructions

Parallel Arithmetic/Logic Unit (ALU) and

Multiplier Execution in a Single Cycle

34K × 32-Bit (1.1M-bit) On-Chip Words of

Dual-Access Static Random-Access

Memory (SRAM) Configured in 2 × 16K plus

2 × 1K Blocks to improve Internal

Performance

Block-Repeat Capability

Zero-Overhead Loops With Single-Cycle

Branches

Conditional Calls and Returns

x5 Phase-Locked Loop (PLL) Clock

Generator

Interlocked Instructions for

Multiprocessing Support

Very Low Power: < 200 mW @ 150 MFLOPS

32-Bit High-Performance CPU

Bus-Control Registers Configure

Strobe-Control Wait-State Generation

16-/32-Bit Integer and 32-/40-Bit

Floating-Point Operations

1.8-V (Core) and 3.3-V (I/O) Supply Voltages

Four Internally Decoded Page Strobes to

Simplify Interface to I/O and Memory

Devices

†

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TImeline and SM320C3x are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443

12 3 4 5 6 7...62

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