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SM320VC33GNLM150 PDF预览

SM320VC33GNLM150

更新时间： 2024-01-23 19:26:28
品牌 Logo 应用领域
德州仪器 - TI 外围集成电路数字信号处理器
页数 文件大小 规格书
54页 608K
描述
DIGITAL SIGNAL PROCESSOR

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SM320VC33GNLM150 技术参数

生命周期：Obsolete零件包装代码：BGA
针数：144Reach Compliance Code：unknown
风险等级：5.84Is Samacsys：N
位大小：32格式：FLOATING POINT
JESD-30 代码：S-XBGA-B144端子数量：144
封装主体材料：CERAMIC封装代码：FBGA
封装等效代码：BGA144,13X13,32封装形状：SQUARE
封装形式：GRID ARRAY, FINE PITCH电源：1.8,3.3 V
认证状态：Not QualifiedRAM（字数）：34816
子类别：Digital Signal Processors表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, MIXEDBase Number Matches：1

SM320VC33GNLM150 数据手册

 浏览型号SM320VC33GNLM150的Datasheet PDF文件第2页浏览型号SM320VC33GNLM150的Datasheet PDF文件第3页浏览型号SM320VC33GNLM150的Datasheet PDF文件第4页浏览型号SM320VC33GNLM150的Datasheet PDF文件第5页浏览型号SM320VC33GNLM150的Datasheet PDF文件第6页浏览型号SM320VC33GNLM150的Datasheet PDF文件第7页 
SM320VC33, SMJ320VC33  
DIGITAL SIGNAL PROCESSOR  
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002  
D High-Performance Floating-Point Digital  
Signal Processor (DSP):  
D On-Chip Memory-Mapped Peripherals:  
- One Serial Port  
- SM/SMJ320VC33-150  
- Two 32-Bit Timers  
- 13-ns Instruction Cycle Time  
- 150 Million Floating-Point Operations  
Per Second (MFLOPS)  
- Direct Memory Access (DMA)  
Coprocessor for Concurrent I/O and CPU  
Operation  
- 75 Million Instructions Per Second  
(MIPS)  
D 164-Pin Low-Profile Quad Flatpack (HFG  
Suffix)  
D 34K × 32-Bit (1.1-Mbit) On-Chip Words of  
Dual-Access Static Random-Access  
Memory (SRAM) Configured in 2 × 16K plus  
2 × 1K Blocks to improve Internal  
Performance  
D 144-Pin Non-hermetic Ceramic Ball Grid  
Array (CBGA) (GNM Suffix)  
D Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
D x5 Phase-Locked Loop (PLL) Clock  
D Two Low-Power Modes  
Generator  
D Two- and Three-Operand Instructions  
D Very Low Power: < 200 mW @ 150 MFLOPS  
D 32-Bit High-Performance CPU  
D Parallel Arithmetic/Logic Unit (ALU) and  
Multiplier Execution in a Single Cycle  
D 16-/32-Bit Integer and 32-/40-Bit  
D Block-Repeat Capability  
Floating-Point Operations  
D Zero-Overhead Loops With Single-Cycle  
D Four Internally Decoded Page Strobes to  
Simplify Interface to I/O and Memory  
Devices  
Branches  
D Conditional Calls and Returns  
D Interlocked Instructions for  
D Boot-Program Loader  
Multiprocessing Support  
D EDGEMODE Selectable External Interrupts  
D 32-Bit Instruction Word, 24-Bit Addresses  
D Eight Extended-Precision Registers  
D Bus-Control Registers Configure  
Strobe-Control Wait-State Generation  
D 1.8-V (Core) and 3.3-V (I/O) Supply Voltages  
D Fabricated Using the 0.18-µm (l -Effective  
eff  
Gate Length) TImelineTechnology by  
Texas Instruments (TI)  
description  
The SM/SMJ320VC33 DSP is a 32-bit, floating-point processor manufactured in 0.18-µm four-level-metal  
CMOS (TImeline) technology. The SM/SMJ320VC33 is part of the SM320C3xgeneration of DSPs from Texas  
Instruments.  
The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and  
flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM/SMJ320VC33  
optimizes speed by implementing functions in hardware that other processors implement through software or  
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TImeline and SM320C3x are trademarks of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL−PRF−38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443  
1234567...54

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