Datasheet > SLG7NT4850

SLG7NT4850

更新时间： 2024-01-29 11:43:11

品牌	Logo	应用领域
DIALOG		/
页数	文件大小	规格书
10页	2003K
描述
APL Power Sequencer

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中文翻译

获取价格

数据手册

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SLG7NT4850 数据手册

SLG7NT4850

APL Power Sequencer

General Description

Pin Configuration

Silego SLG7NT4850 is a low power and small form

device. The SoC is housed in a 2mm x 3mm

STQFN package which is optimal for using with

small devices.

Features

VDD

VNN_PGD

VCCST_PWRGD

VCCST

• Low Power Consumption

• Pb-Free / RoHS Compliant

• Halogen-Free

WAKE

PWRBTN#

AC_PRESENT_SOC

AC_OK_CHGR

SKL_APL_N

• STQFN-20 Package

SLP_S3_N

VCCSTG

Output Summary

• 8 Outputs — Open Drain NMOS 1X

DDR_VR_PWRGD

GND

SLP_S0ix_N

STQFN-20

TOP VIEW

Silego Technology, Inc.

Rev 1.02

Revised March 11, 2016

SLG7NT4850_DS_r102

SLG7NT4850_GP_r003

12 3 4 5 6 7...10

中文翻译

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