Datasheet > SLGSSTU32864EX

SLGSSTU32864EX

更新时间： 2024-01-11 06:47:20

品牌	Logo	应用领域
其他 - ETC		双倍数据速率
页数	文件大小	规格书
11页	207K
描述
DDR2 Configurable Registered Buffer

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数据手册

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SLGSSTU32864EX 数据手册

SLGSSTU32864E

DDR2 Configurable Registered Buffer

Applications:

Features:

•

PC3200/4300 DDR2 memory modules

1:1 25-bit or 1:2 14-bit configurable registered

buffer

•

Compatible with JEDEC standard SSTU32864

Differential Clock inputs

SSTL_18 Clock and data input signaling

Output circuitry minimizes effects of SSO

and unterminated lines

•

1.8V data registers

•

LVCMOS input levels on control and RESET pins

1.7V-1.9V Supply voltage range.

Max Clock frequency > 300MHz

General Description

The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range.

When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the

SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A

configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS

input levels.The C0,C1 input pins are not intended to be switched dynamically during normal operation.

They should be tied to logic high or low levels to configure the register.

Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signals. The

rising edge of CLK (crossing with CLK falling) is used to register the Data. All inputs are SSTL_18 except

C0,C1, and RESET pins.

The SLGSSTU32864 supports low-power standby operation. Setting RESET pin to a logic “low” disables

(CLK/CLK) receivers, and allows floating inputs to all other receivers as well (D, V

, CLK/CLK). Addi-

REF

tionally, all internal registers are reset, and outputs (Q) are set “low”. RESET input pin must always be

driven to a valid logic state “high” or “low”.

RESET, an LVCMOS asynchronous signal, is also intended for use at the time of power-up. RESET must

be held at a logic “low” level during power up. This ensures defined outputs before a stable CLK/CLK is

supplied.

The SLGSSTU32864 supports low-power active operation as it monitors DCS and CSR inputs. The Qn

outputs will be prevented from changing states when both DCS and CSR inputs are high. The Qn outputs

will be allowed to change state if either one of DCS or CSR inputs is low. If DCS control is not desired,

then CSR input should be held low. In that case, the setup and hold times of DCS is the same as the other

D inputs.

Ordering Information:

Package type

Package suffix

Topside marking

Ordering code

LFBGA-96ball

SLGSSTU32864EX

SLGSSTU32864EX-TR

(2,000 pcs/tape and reel)

13.5 X 5.5 mm body

LFBGA-96ball

SLGSSTU32864EX

SLGSSTU32864EX (2,000

pcs/tray)

13.5 X 5.5 mm body

Silego Technology Inc.

(408) 327-8800

PRELIMINARY

Data is subject to change.

Mar 5, 2004

12 3 4 5 6 7...11

中文翻译

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与SLGSSTU32864EX相关器件

型号	品牌	获取价格	描述	数据表
SLGSSTU32864EX-TR	ETC	获取价格	DDR2 Configurable Registered Buffer
SLGSSTVF16859	ETC	获取价格	DDR 13 to 26 Bit Registered Buffer
SLGSSTVF16859H	ETC	获取价格	DDR 13 to 26 Bit Registered Buffer
SLGSSTVF16859H-TR	ETC	获取价格	DDR 13 to 26 Bit Registered Buffer
SLGSSTVF16859V	ETC	获取价格	DDR 13 to 26 Bit Registered Buffer
SLGSSTVF16859V-TR	ETC	获取价格	DDR 13 to 26 Bit Registered Buffer
SLH_W20N50S	Maplesemi	获取价格	TO-247&TO-3P
SLH_W9N90C	Maplesemi	获取价格	TO-247&TO-3P
SLH-010	HITACHI	获取价格	Splitter And Combiner, 1dB Insertion Loss-Max, CHIP-3
SLH-010-1.50-G-D	SAMTEC	获取价格	Board Connector

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