Datasheet > SLG7NT4805

SLG7NT4805

更新时间： 2024-01-24 14:23:27

品牌	Logo	应用领域
DIALOG		/
页数	文件大小	规格书
8页	213K
描述
DPWROK and RSMRST_N Logic

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中文翻译

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数据手册

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SLG7NT4805 数据手册

SLG7NT4805

DPWROK and RSMRST_N Logic

General Description

Pin Configuration

Silego SLG7NT4805 is a low power and small

form device. The SoC is housed in a 2mm x 3mm

STQFN package which is optimal for using with

small devices.

Features

VDD

PS_ON_N

• Low Power Consumption

• Pb-Free / RoHS Compliant

• Halogen-Free

SLP_S4_N

XDP_PRST_N

DPWROK

SLP_S3_N

H_SKTOCC_N

V3.3A_PWRGD

V5DSW

• STQFN-20 Package

RSMRST_N

V5A_FET_CTRL

V3A_FET_CTRL

GND

Output Summary

• 8 Outputs — Open Drain NMOS 1X

V3.3DSW_PWRGD

STQFN-20

TOP VIEW

Silego Technology, Inc.

Rev 1.01

Revised March 08, 2016

SLG7NT4805_DS_r101

SLG7NT4805_GP_r006

12 3 4 5 6 7 8

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