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SIT9156AI-2D2-33E156.250000

更新时间： 2025-07-19 19:51:23
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频率(MHz):156.25 MHz;最小工作温度(℃）:-40°C;最大工作温度(℃）:85°C;安装类型:表面贴装型;封装:6-SMD，无引线;

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SIT9156AI-2D2-33E156.250000 数据手册

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SiT9156  
LVPECL, LVDS Oscillator (XO) with 0.3 ps Jitter for 10Gb Ethernet  
The Smart Timing Choice  
Features  
Applications  
0.3 ps RMS phase jitter (random) for 10GbE applications  
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,  
PCI-Express  
Frequency stability as low as ±10 ppm  
100% drop-in replacement for quartz and SAW oscillators  
Configurable positive frequency shift, +25, +50, or +75 ppm  
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mmxmm  
Industrial and extended commercial temperature ranges  
Best in class 1-year and 10-year aging  
Telecom, networking, instrumentation, storage, servers  
Best resilience, up to 40x better than quartz  
For other frequencies, refer to SiT9121 or 9122 datasheet  
Electrical Characteristics  
Parameter and Conditions  
Symbol  
Min.  
Typ.  
Max.  
Unit  
Condition  
LVPECL and LVDS, Common Electrical Characteristics  
Supply Voltage  
Vdd  
2.97  
2.25  
2.25  
3.3  
2.5  
–
3.63  
2.75  
3.63  
V
V
V
Termination schemes in Figures 1 and 2 - XX ordering code  
Output Frequency Range  
Frequency Stability  
f
156.25000, 156.253906,  
156.257812, 156.261718,  
161.132800  
MHz  
156.253906 MHz, +25 PPM from 156.250000  
156.257812 MHz, +50 PPM from 156.250000  
156.261718 MHz, +75 PPM from 156.250000  
F_stab  
-10  
–
–
–
–
–
–
–
–
–
–
+10  
ppm  
ppm  
ppm  
ppm  
ppm  
ppm  
°C  
-20  
-25  
-50  
-2  
+20  
+25  
+50  
+2  
Inclusive of initial tolerance, operating temperature, rated power  
supply voltage, and load variations  
First Year Aging  
F_aging1  
F_aging10  
T_use  
25°C  
10-year Aging  
-5  
+5  
25°C  
Operating Temperature Range  
-40  
-20  
70%  
–
+85  
+70  
–
Industrial  
°C  
Extended Commercial  
Input Voltage High  
VIH  
VIL  
Vdd  
Vdd  
Pin 1, OE or ST  
Input Voltage Low  
30%  
Pin 1, OE or ST  
Input Pull-up Impedance  
Z_in  
–
2
–
100  
–
250  
–
kΩ  
MΩ  
ms  
Pin 1, OE logic high or logic low, or ST logic high  
Pin 1, ST logic low  
Start-up Time  
Resume Time  
Duty Cycle  
T_start  
T_resume  
DC  
6
10  
Measured from the time Vdd reaches its rated minimum value.  
In Standby mode, measured from the time ST pin crosses  
50% threshold.  
–
6
10  
ms  
45  
–
55  
%
Contact SiTime for tighter duty cycle  
LVPECL, DC and AC Characteristics  
Current Consumption  
OE Disable Supply Current  
Output Disable Leakage Current  
Standby Current  
Idd  
I_OE  
I_leak  
I_std  
–
61  
–
69  
35  
mA  
mA  
A  
A  
mA  
V
Excluding Load Termination Current, Vdd = 3.3V or 2.5V  
–
OE = Low  
OE = Low  
–
–
1
–
–
–
100  
ST = Low, for all Vdds  
Maximum Output Current  
Output High Voltage  
I_driver  
VOH  
–
30  
Maximum average current drawn from OUT+ or OUT-  
See Figure 1(a)  
Vdd-1.1  
Vdd-1.9  
1.2  
–
Vdd-0.7  
Vdd-1.5  
2.0  
Output Low Voltage  
VOL  
–
V
See Figure 1(a)  
Output Differential Voltage Swing V_Swing  
1.6  
300  
V
See Figure 1(b)  
Rise/Fall Time  
Tr, Tf  
–
500  
ps  
20% to 80%, see Figure 1(a)  
OE Enable/Disable Time  
T_oe  
T_phj  
–
–
–
120  
0.3  
ns  
ps  
f = 156.25 MHz - For other frequencies, T_oe = 100ns + 3 period  
IEEE802.3-2005 10GbE jitter measurement specifications  
RMS Phase Jitter (random)  
0.25  
LVDS, DC and AC Characteristics  
Current Consumption  
Idd  
–
–
47  
–
55  
35  
mA  
mA  
mV  
Excluding Load Termination Current, Vdd = 3.3V or 2.5V  
OE Disable Supply Current  
Differential Output Voltage  
I_OE  
VOD  
OE = Low  
250  
350  
450  
See Figure 2  
SiTime Corporation  
Rev. 1.06  
990 Almanor Avenue, Sunnyvale, CA 94085  
(408) 328-4400  
www.sitime.com  
Revised October 6, 2014  
12345678

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