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SI1001

更新时间： 2024-02-05 03:11:06
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
376页 2369K
描述
Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver

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SI1001 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：QCCN, LCC42,.2X.27,27/20Reach Compliance Code：unknown
风险等级：5.84位大小：8
CPU系列：8051JESD-30 代码：R-PQCC-N42
端子数量：42最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC42,.2X.27,27/20
封装形状：RECTANGULAR封装形式：CHIP CARRIER
电源：1.8/3.6 V认证状态：Not Qualified
RAM（字节）：4352ROM（单词）：32768
ROM可编程性：FLASH速度：25 MHz
子类别：Microcontrollers最大压摆率：5 mA
表面贴装：YES温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUADBase Number Matches：1

SI1001 数据手册

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Si1000/1/2/3/4/5  
Ultra Low Power, 64/32 kB, 10-Bit ADC  
®
MCU with Integrated 240–960 MHz EZRadioPRO Transceiver  
EZRadioPRO® Transceiver  
Ultra Low Power: 0.9 to 3.6 V Operation  
-
Typical sleep mode current < 0.1 µA; retains state and  
RAM contents over full supply range; fast wakeup of < 2 µs  
Less than 600 nA with RTC running  
Less than 1 µA with RTC running and radio state retained  
On-chip dc-dc converter allows operation down to 0.9 V.  
-
-
-
-
Frequency range = 240–960 MHz  
Sensitivity = –121 dBm  
FSK, GFSK, and OOK modulation  
Max output power = +20 dBm (Si1000/1), +13 dBm  
(Si1002/3/4/5)  
-
-
-
-
Two built-in brown-out detectors cover sleep and active  
modes  
-
RF power consumption  
- 18.5 mA receive  
10-Bit Analog to Digital Converter  
- 18 mA @ +1 dBm transmit  
- 30 mA @ +13 dBm transmit  
- 85 mA @ +20 dBm transmit  
Data rate = 0.123 to 256 kbps  
Auto-frequency calibration (AFC)  
Antenna diversity and transmit/receive switch control  
Programmable packet handler  
TX and RX 64 byte FIFOs  
-
-
-
Up to 300 ksps  
Up to 18 external inputs  
External pin or internal VREF (no external capacitor  
required)  
-
-
-
-
-
-
-
-
-
-
Built-in temperature sensor  
External conversion start input option  
Autonomous burst mode with 16-bit automatic averaging  
accumulator  
Frequency hopping capability  
On-chip crystal tuning  
Dual Comparators  
-
-
-
Programmable hysteresis and response time  
Configurable as interrupt or reset source  
Low current (< 0.5 µA)  
Digital Peripherals  
-
19 or 16 port I/O plus 3 GPIO pins; Hardware enhanced  
UART, SPI, and I2C serial ports available concurrently  
Low power 32-bit SmaRTClock  
On-Chip Debug  
-
-
-
On-chip debug circuitry facilitates full-speed, non-intrusive  
in-system debug (No emulator required)  
Four general purpose 16-bit counter/timers; six channel  
programmable counter array (PCA)  
-
-
-
Provides breakpoints, single stepping  
Inspect/modify memory and registers  
Complete development kit  
Clock Sources  
-
Precision internal oscillators: 24.5 MHz with ±2% accuracy  
supports UART operation; spread-spectrum mode for  
reduced EMI; Low power 20 MHz internal oscillator  
High-Speed 8051 µC Core  
-
Pipelined instruction architecture; executes 70% of instruc-  
tions in 1 or 2 system clocks  
-
-
-
External oscillator: Crystal, RC, C, CMOS clock  
SmaRTClock oscillator: 32.768 kHz crystal or self-oscillate  
Can switch between clock sources on-the-fly; useful in  
implementing various power saving modes  
-
-
Up to 25 MIPS throughput with 25 MHz clock  
Expanded interrupt handler  
Memory  
Package  
-
-
4352 bytes internal data RAM (256 + 4096)  
64 kB (Si1000/2/4) or 32 kB (Si1001/3/5) Flash; In-system  
programmable in 1024-byte sectors—1024 bytes are  
reserved in the 64 kB devices  
-
42-pin QFN (5 x 7 mm)  
Temperature Range: –40 to +85 °C  
ANALOG  
PERIPHERALS  
DIGITAL I/O  
EZRadioPRO  
(240–960 MHz)  
UART  
SMBus  
SPI  
Port 0  
EZRadio  
PRO  
Serial  
LNA  
A
M
U
X
10-bit  
IREF  
PCA  
300 ksps  
ADC  
Timer 0  
Timer 1  
Timer 2  
Timer 3  
CRC  
Interface  
Port 1  
PA  
+
–
+
VREF  
TEMP  
SENSOR  
–
Mixer  
PGA  
ADC  
Port 2  
VREG  
VOLTAGE  
COMPARATORS  
24.5 MHz PRECISION  
20 MHz LOW POWER  
INTERNAL OSCILLATOR  
INTERNAL OSCILLATOR  
Digital  
Modem  
External Oscillator  
HARDWARE smaRTClock  
PLL  
Delta  
Sigma  
HIGH-SPEED CONTROLLER CORE  
Modulator  
64/32 kB  
ISP FLASH  
FLEXIBLE  
INTERRUPTS  
8051 CPU  
(25 MIPS)  
DEBUG  
4352 B  
SRAM  
OSC  
Digital  
Logic  
POR WDT  
CIRCUITRY  
Rev. 1.0 9/10  
Copyright © 2010 by Silicon Laboratories  
Si1000/1/2/3/4/5  
1234567...376

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