preliminary Data Sheet
Rev.0.9
22.07.2013
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Row
Addr.
Device Bank
Addr.
Col.
Addr.
Module
Bank Select
Organization
DDR3 SDRAMs used
Refresh
512M x 64bit
8 x 512M x 8bit (4Gbit)
16
BA0, BA1, BA2
10
8k
S0#
Module Dimensions
in mm
133.35 (long) x 30(high) x 2.70[max] (thickness)
Timing Parameters
Module
Part Number
Transfer Rate Clock Cycle / Data bit rate
Latency
Density
4GByte
4GByte
SGU04G64A1BE1MT-BBR
SGU04G64A1BE1MT-CCR
SGU04G64A1BE1MT-DCR
8.5 GB/s
10.6 GB/s
12.8 GB/s
1.87ns / 1066MT/s
1.5ns / 1333MT/s
1.25ns / 1600MT/s
7-7-7
9-9-9
4GByte
11-11-11
Pin Name
A0 – A9, A11 – A15
A10/AP
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
BA0, BA1, BA2
DQ0 – DQ63
DM0 – DM7
RAS#
Input Data Mask
Row Address Strobe
Column Address Strobe
Write Enable
CAS#
WE#
CKE0
Clock Enable
CK0
Clock Inputs, positive line
Clock Inputs, negative line
Data Strobe, positive line
CK0#
DQS0 – DQS7
DQS0# – DQS7#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
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