Datasheet > SGU02G72H1BG2SA-CCRT

SGU02G72H1BG2SA-CCRT

更新时间： 2022-02-26 13:26:16

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其他 - ETC		动态存储器双倍数据速率
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2048MB DDR3 â SDRAM Ultra Low Profile ECC DIMM

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SGU02G72H1BG2SA-CCRT 数据手册

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Data Sheet

Rev.1.0

04.02.2011

I_DDSpecifications and Conditions

(0°C ≤ T_CASE≤ + 85°C; V_DDQ= +1.5V ± 0.075V, V_DD= +1.5V ± 0.075V)

Parameter

& Test Condition

max.

Symbol

I_DD0

Unit

10600-999

8500-777

OPERATING CURRENT *) :

One device bank Active-Precharge;

405

t_RC= t_RC(I_DD); t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

I_OUT= 0mA; BL = 4, CL = CL (I_DD), AL = 0;

t_CK= t_CK(I_DD), t_RC= t_RC(I_DD), t_RAS= t_RASMIN (I_DD),

t_RCD= t_RCD(I_DD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as I_DD4W

I_DD1

468

450

Fast Exit

PRECHARGE POWER-DOWN

I_DD2P

216

180

270

216

180

270

CURRENT:

All device banks idle; Power-down mode;

Slow Exit

t_CK= t_CK(I_DD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at V_REF

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at V_REF

PRECHARGE STANDBY CURRENT:

All device banks idle;

I_DD2Q

I_DD2N

270

t_CK= t_CK(I_DD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

ACTIVE POWER-DOWN CURRENT:

I_DD3P

270

360

270

360

All device banks open; t_CK= t_CK(I_DD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at V_REF(always fast exit)

ACTIVE STANDBY CURRENT:

All device banks open; t_CK= t_CK(I_DD),

I_DD3N

t_RAS= t_RASMAX (I_DD), t_RP= t_RP(I_DD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

OPERATING READ CURRENT:

I_DD4R

720

630

All device banks open, Continuous burst reads; One

module rank active; I_OUT= 0mA; BL = 4, CL = CL (I_DD),

AL = 0; t_CK= t_CK(I_DD), t_RAS= t_RASMAX (I_DD), t_RP= t_RP

(I_DD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

Swissbit AG

Industriestrasse 4

CH-9552 Bronschhofen

Fon: +41 (0) 71 913 03 03

Fax: +41 (0) 71 913 03 15

www.swissbit.com

eMail: info@swissbit.com

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