ACS8525 LC/P
Line Card Protection Switch for
SONET/SDH Systems
ADVANCED COMMUNICATIONS
Description
FINAL
Features
DATASHEET
The ACS8525 is a highly integrated, single-chip solution
for “Hit-less” protection switching of SEC (SDH/SONET
Equipment Clock) + Sync clock “Groups”, from Master
and Slave SETS clock cards and a third (Stand-by) source,
for Line Cards in a SONET or SDH Network Element. The
ACS8525 has fast activity monitors on the SEC clock
inputs and will implement automatic system protection
switching against the Master clock failure. The selection
of the Master/Slave input can be forced by a Force Fast
Switch pin. If both the Master and Slave input clocks fail,
the Stand-by “Group” is selected or, if no Stand-by is
available, the device enters Digital Holdover mode.
SONET/SDH applications up to OC-3/STM-1 bit rates
Switches between grouped inputs (SEC/Sync pairs)
Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz
multiples up to 155.52 MHz), plus Frame Sync/Multi-
Frame Sync
Outputs: two SEC clocks at any of several spot
frequencies from 2 kHz up to 77.76 MHz via the
TTL/CMOS port and up to 311.04 MHz via the
PECL/LVDS port
Selectable clock I/O port technologies
Modes for E3/DS3 and multiple E1/DS1 rate output
clocks
The ACS8525 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
Frequency translation of SEC input clock to a different
local line card clock
Robust input clock source activity monitoring on all
Master and Slave SEC inputs to the device support
TTL/CMOS and PECL/LVDS. The Stand-by SEC and three
Sync inputs are TTL/CMOS only.
inputs
Supports Free-run, Locked and Digital Holdover
modes of operation
The ACS8525 generates two SEC clock outputs, via one
PECL/LVDS and one TTL/CMOS port, with spot
Automatic “Hit-less” source switchover on loss of
input
frequencies from 2 kHz up to 311.04 MHz (up to 155.52
MHz on the TTL/CMOS port). It also provides an 8 kHz
Frame Sync and a 2 kHz Multi-Frame Sync signal output
with programmable pulse width and polarity.
External force fast switch between SEC1/SEC2 inputs
Phase Build-out for output clock phase continuity
during input switchover
PLL “Locked” and “Acquisition” bandwidths
The ACS8525 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
individually selectable from 18, 35 or 70 Hz
Serial interface for device set-up
Single 3.3 V operation, 5 V I/O compatible
Operating temperature (ambient) of -40 to +85°C
Available in LQFP 64 package
IEEE 1149.1 JTAG Boundary Scan is supported.
Lead (Pb)-free version available (ACS8525T), RoHS
Block Diagram
and WEEE compliant
Figure 1 Block Diagram of the ACS8525 LC/P
3 x SEC/Sync Input Groups
SEC1 & SEC2:
TTL/PECL/LVDS,
SEC3 and all Syncs
SEC Outputs:
DPLL1
DPLL2
TTL only
SEC1
01 (PECL/LVDS)
Master
Slave
MUX
2
Input
SEC Port
Monitors
and
Input
Selection
Control
APLL2
SYNC1
02 (TTL)
Output
Port
Frequency
Selection
SEC2
Digital Feedback
APLL3
Selector
SYNC2
Sync Outputs:
E1/DS1
Synthesis
MFrSync 2 kHz (TTL)
SEC3
MUX
1
APLL 1
Stand-by
FrSync 8 kHz (TTL)
SYNC3
01 and 02:
SEC Inputs:
Programmable
Frequencies
2 kHz, 4 kHz,
N x 8 kHz
E1/DS1 (2.048/1.544 MHz)
and frequency multiples:
1.5x, 2x, 3x, 4x, 6x, 12x,
16x, and 24x E1/DS1
TCK
TDI
TMS
TRST
TDO
Chip
Clock
Generator
IEEE
1149.1
JTAG
E3/DS3, 2 kHz, 8 kHz.
Priority
Table
Serial Interface
Port
1.544/2.048 MHz
6.48 MHz
Register Set
and OC-N* rates: OC-1 51.84 MHz
OC-3 155.52 MHz and derivatives:
6.48 MHz (O2 port only)
19.44 MHz, 25.92 MHz,
38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz (01 port only)
311.04 MHz (01 port only)
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
TCXO or
XO
155.52 MHz
F8525D_001BLOCKDIA_05
Revision 3.01/August 2005 © Semtech Corp.
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