ACS8530 SETS
Synchronous Equipment Timing Source for
Stratum 2/3E Systems
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Description
Features
The ACS8530 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8530 is fully
compliant with the required international specifications
and standards.
Suitable for Stratum 2, 3E, 3, 4E and 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications (to Telcordia 1244-CORE[19]
Stratum 3E, and GR-253[17], and ITU-T G.812[10]
Type III and G.813[11] specifications)
Accepts 14 individual input reference clocks, all with
robust input clock source quality monitoring
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8530 generates independent
SEC and BITS clocks, an 8 kHz Frame Synchronization
clock and a 2 kHz Multi-Frame Synchronization clock.
Simultaneously generates nine output clocks, plus
two sync pulse outputs
Absolute Holdover accuracy better than 3 x 10-10
(manual), 7.5 x 10-14 (instantaneous); Holdover
stability defined by choice of external XO
Programmable PLL bandwidth, for wander and jitter
tracking/attenuation, 0.5 mHz to 70 Hz in 18 steps
Two ACS8530 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8530 failure.
Automatic hit-less source switchover on loss of input
Phase Transient Protection and Phase Build-out on
locked to reference and on reference switching
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring. The ACS8530 supports IEEE 1149.1[5]
JTAG boundary scan.
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, or boot from EPROM
Output phase adjustment in 6 ps steps up to ±200 ns
IEEE 1149.1 JTAG[5] Boundary Scan
Single 3.3 V operation. 5 V tolerant
Block Diagram
Available in LQFP 100 package
Lead (Pb) - free version available (ACS8530T), RoHS
and WEEE compliant.
Figure 1 Block Diagram of the ACS8530 SETS
Outputs
T01-TO7:
E1/DS1 (2.048/
T4 DPLL/Freq. Synthesis
1.544 MHz)
and frequency
multiples:
1.5 x, 2 x, 3 x
4 x, 6 x, 12 x
16 x and 24 x
E3/DS3
Output
Ports
T4 APLL
Digital
Loop
Filter
PFD
DTO
Optional
Frequency
Dividers
TO1
to
TO7
T4
Selector
2 x AMI
10 x TTL
2 x PECL/LVDS
Programmable;
64/8 kHz (AMI)
2 kHz
Divider, 1/n
14
n = 1 to 2
2 kHz
8 kHz
Input
Port
Monitors
and
and OC-N* rates
TO8
&
TO9
4 kHz
T08: AMI
TO9: E1/DS1
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
Selection
Control
T0 DPLL/Freq. Synthesis
T0 APLL
(output)
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
14 x SEC
TO10: 8 kHz
(FrSync)
TO11: 2 kHz
(MFrSync)
TO10
&
TO11
Frequency
Dividers
Optional
T0
Selector
Divider, 1/n
Digital
Loop
Filter
14
n = 1 to 2
PFD
DTO
TO APLL
(feedback)
OC-N* rates =
OC-1 51.84 MHz
OC-3 155.52 MHz
and derivatives:
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
TCK
TDI
TMS
TRST
TDO
Chip
Clock
Generator
IEEE
1149.1
JTAG
Priority
Table
Microprocessor
Port
Register Set
77.76 MHz
155.52 MHz
311.04 MHz
OCXO
F8530D_001BLOCKDIA_09
Revision 3.02/November 2005 © Semtech Corp.
Page1
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