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SD520YS-T3 PDF预览

SD520YS-T3

更新时间: 2024-11-18 22:08:39
品牌 Logo 应用领域
WTE 整流二极管瞄准线功效
页数 文件大小 规格书
3页 47K
描述
5.0A DPAK SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER

SD520YS-T3 数据手册

 浏览型号SD520YS-T3的Datasheet PDF文件第2页浏览型号SD520YS-T3的Datasheet PDF文件第3页 
WTE  
POWER SEMICONDUCTORS  
SD520YS – SD5100YS  
5.0A DPAK SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER  
Features  
!
Schottky Barrier chip  
A
B
C
J
!
!
!
!
!
!
Guard Ring Die Construction  
Low Profile Package  
D
High Surge Current Capability  
Low Power Loss, High Efficiency  
Ideal for Printed Circuit Board  
For Use in Low Voltage, High Frequency  
Inverters, Free Wheeling Applications  
E
PIN 1  
2
3
K
G
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ H  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ L  
P
P
D PAK/TO-252AA  
Mechanical Data  
Dim  
A
B
C
D
E
Min  
6.4  
5.0  
2.35  
Max  
!
!
Case: Molded Plastic  
6.8  
5.4  
Terminals: Plated Leads Solderable per  
MIL-STD-750, Method 2026  
Polarity: Cathode Band  
PIN 1 -  
PIN 3 -  
+
2.75  
1.60  
5.7  
!
!
!
!
!
Case PIN 2  
5.3  
2.3  
0.4  
0.4  
0.3  
Weight: 0.4 grams (approx.)  
Mounting Position: Any  
G
H
J
2.7  
0.8  
Marking: Type Number  
0.6  
Standard Packaging: 16mm Tape (EIA-481)  
K
L
0.7  
0.50 Typical  
P
2.3  
All Dimensions in mm  
Maximum Ratings and Electrical Characteristics @TA=25°C unless otherwise specified  
Single Phase, half wave, 60Hz, resistive or inductive load. For capacitive load, derate current by 20%.  
SD  
SD  
SD  
SD  
SD  
SD  
SD  
Characteristic  
Symbol  
Unit  
520YS 530YS 540YS 550YS 560YS 580YS 5100YS  
Peak Repetitive Reverse Voltage  
Working Peak Reverse Voltage  
DC Blocking Voltage  
VRRM  
VRWM  
VR  
20  
14  
30  
21  
40  
28  
50  
60  
42  
80  
56  
100  
70  
V
RMS Reverse Voltage  
VR(RMS)  
IO  
35  
V
A
Average Rectified Output Current  
@TL = 75°C  
5.0  
Non-Repetitive Peak Forward Surge Current 8.3ms  
Single half sine-wave superimposed on rated load  
(JEDEC Method)  
I
FSM  
100  
A
Forward Voltage (Note 1)  
@IF = 5.0A  
VFM  
IRM  
0.55  
0.75  
0.85  
V
Peak Reverse Current  
At Rated DC Blocking Voltage  
@TA = 25°C  
@TA = 100°C  
0.2  
20  
mA  
Typical Junction Capacitance (Note 2)  
Typical Thermal Resistance Junction to Ambient  
Operating Temperature Range  
Cj  
RJA  
Tj  
400  
50  
pF  
K/W  
°C  
-50 to +125  
-50 to +150  
Storage Temperature Range  
TSTG  
°C  
Note: 1. Mounted on P.C. Board with 14mm2 (0.13mm thick) copper pad.  
2. Measured at 1.0 MHz and applied reverse voltage of 4.0V D.C.  
SD520YS – SD5100YS  
1 of 3  
© 2002 Won-Top Electronics  

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