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SCANSTA112VS PDF预览

SCANSTA112VS

更新时间: 2024-02-28 07:12:17
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器微控制器和处理器外围集成电路uCs集成电路uPs集成电路
页数 文件大小 规格书
15页 299K
描述
7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer

SCANSTA112VS 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:TFQFP, TQFP100,.63SQ针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.13
外部数据总线宽度:JESD-30 代码:S-PQFP-G100
JESD-609代码:e4长度:14 mm
湿度敏感等级:3端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TFQFP
封装等效代码:TQFP100,.63SQ封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Microprocessor ICs
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUITBase Number Matches:1

SCANSTA112VS 数据手册

 浏览型号SCANSTA112VS的Datasheet PDF文件第3页浏览型号SCANSTA112VS的Datasheet PDF文件第4页浏览型号SCANSTA112VS的Datasheet PDF文件第5页浏览型号SCANSTA112VS的Datasheet PDF文件第7页浏览型号SCANSTA112VS的Datasheet PDF文件第8页浏览型号SCANSTA112VS的Datasheet PDF文件第9页 
TABLE 1. Pin Descriptions  
No.  
Pin Name  
VCC  
Pins  
10  
10  
1
I/O  
Description  
N/A Power  
N/A Ground  
GND  
RESET  
I
I
I
RESET Input: will force a reset of the device regardless of the current state.  
ADDRESS MASK input: Allows masking of lower slot input pins.  
ADDMASK  
MPselB1/B0  
1
1
MASTER PORT SELECTION: Controls selection of LSPB0 or LSPB1 as the backplane port.  
The unselected port becomes LSP00. A value of "0" will select LSPB0 as the master port.  
Selects ScanBridge or Stitcher Mode.  
SB/S  
1
7
1
I
I
I
LSPsel  
In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain  
Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit  
of the control register at power-up. This value is used to control the presence of registers  
and pad-bits in the scan chain while in the stitcher mode.  
(0-6)  
TRANS  
TLR_TRST  
1
I
Sets the driven value of TRST0-5 when LSP TAPs are in TLR and the device is not being  
reset. During RESET = "0" or TRSTB = "0" (IgnoreReset = "0") TRSTn = "0". This pin is to be  
tied low to match the function of the SCANSTA111  
TLR_TRST6  
TDIB0, TDIB1  
1
2
I
I
This pin affects TRST of LSP6 only. This pin is to be tied low to match the function of the  
SCANSTA111  
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112  
through this input pin. MPselB1/B0 determines which port is the master backplane port and  
which is LSP00. This input has a 25Kinternal pull-up resistor and no ESD clamp diode  
(ESD is controlled with an alternate method). When the device is power-off (VDD floating),  
this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not  
floating but tied to VSS) this input appears to be a capacitive load with the pull-up to ground.  
TMSB0, TMSB1  
2
I/O BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the  
’STA112. Also controls sequencing of the TAPs which are on the local scan chains.  
MPselB1/B0 determines which port is the master backplane port and which is LSP00. This  
bidirectional TRISTATE pin has 24mA of drive current, with a 25Kinternal pull-up resistor  
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is  
power-off (VDD floating), this input appears to be a capacitive load to ground (Note 1). When  
VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the  
pull-up to ground.  
TDOB0, TDOB1  
2
2
I/O BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the  
local TAPs, back toward the scan master controller. This bidirectional TRISTATE pin has  
12mA of drive current. MPselB1/B0 determines which port is the master backplane port and  
which is LSP00. Output is sampled during interrogation addressing. When the device is  
power-off (VDD = 0V or floating), this output appears to be a capacitive load (Note 1).  
I/O TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls  
all scan operations of the ’STA112 and of the local scan ports. MPselB1/B0 determines which  
port is the master backplane port and which is LSP00. These bidirectional TRISTATE pins  
have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD  
clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD  
floating), this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.;  
not floating but tied to VSS) this input appears to be a capacitive load to ground.  
I/O TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic.  
MPselB1/B0 determines which port is the master backplane port and which is LSP00. This  
bidirectional TRISTATE pin has 24mA of drive current, with a 25Kinternal pull-up resistor  
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is  
power-off (VDD floating), this pin appears to be a capacitive load to ground (Note 1). When  
VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the  
pull-up to ground.  
TCKB0, TCKB1  
TRSTB0, TRSTB1  
2
www.national.com  
6

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