TABLE 1. Pin Descriptions
No.
Pin Name
VCC
Pins
10
10
1
I/O
Description
N/A Power
N/A Ground
GND
RESET
I
I
I
RESET Input: will force a reset of the device regardless of the current state.
ADDRESS MASK input: Allows masking of lower slot input pins.
ADDMASK
MPselB1/B0
1
1
MASTER PORT SELECTION: Controls selection of LSPB0 or LSPB1 as the backplane port.
The unselected port becomes LSP00. A value of "0" will select LSPB0 as the master port.
Selects ScanBridge or Stitcher Mode.
SB/S
1
7
1
I
I
I
LSPsel
In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain
Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit
of the control register at power-up. This value is used to control the presence of registers
and pad-bits in the scan chain while in the stitcher mode.
(0-6)
TRANS
TLR_TRST
1
I
Sets the driven value of TRST0-5 when LSP TAPs are in TLR and the device is not being
reset. During RESET = "0" or TRSTB = "0" (IgnoreReset = "0") TRSTn = "0". This pin is to be
tied low to match the function of the SCANSTA111
TLR_TRST6
TDIB0, TDIB1
1
2
I
I
This pin affects TRST of LSP6 only. This pin is to be tied low to match the function of the
SCANSTA111
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112
through this input pin. MPselB1/B0 determines which port is the master backplane port and
which is LSP00. This input has a 25KΩ internal pull-up resistor and no ESD clamp diode
(ESD is controlled with an alternate method). When the device is power-off (VDD floating),
this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.; not
floating but tied to VSS) this input appears to be a capacitive load with the pull-up to ground.
TMSB0, TMSB1
2
I/O BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
’STA112. Also controls sequencing of the TAPs which are on the local scan chains.
MPselB1/B0 determines which port is the master backplane port and which is LSP00. This
bidirectional TRISTATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (VDD floating), this input appears to be a capacitive load to ground (Note 1). When
VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the
pull-up to ground.
TDOB0, TDOB1
2
2
I/O BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the
local TAPs, back toward the scan master controller. This bidirectional TRISTATE pin has
12mA of drive current. MPselB1/B0 determines which port is the master backplane port and
which is LSP00. Output is sampled during interrogation addressing. When the device is
power-off (VDD = 0V or floating), this output appears to be a capacitive load (Note 1).
I/O TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the ’STA112 and of the local scan ports. MPselB1/B0 determines which
port is the master backplane port and which is LSP00. These bidirectional TRISTATE pins
have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD
clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD
floating), this input appears to be a capacitive load to ground (Note 1). When VDD = 0V (i.e.;
not floating but tied to VSS) this input appears to be a capacitive load to ground.
I/O TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic.
MPselB1/B0 determines which port is the master backplane port and which is LSP00. This
bidirectional TRISTATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (VDD floating), this pin appears to be a capacitive load to ground (Note 1). When
VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the
pull-up to ground.
TCKB0, TCKB1
TRSTB0, TRSTB1
2
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