Preliminary
®
SC3053B
•
•
•
•
•
Quartz SAW Frequency Stability
Fundamental Fixed Frequency
Very Low Jitter and Power Consumption
Rugged, Miniature, Surface-Mount Case
Low-Voltage Power Supply (3.3 VDC)
750.0 MHz
Differential
Sine-Wave
Clock
This digital clock is designed for use with high-speed timing systems. Fundamental-mode oscillation is made
possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low
power consumption. Differential outputs provide a sine wave that is capable of driving 50 W loads.
Rating
Value
Units
VDC
VDC
°C
Power Supply Voltage (V at Terminal 1)
0 to +4.0
0 to +4.0
-40 to +85
CC
Input Voltage (ENABLE at Terminal 8)
Case Temperature (Powered or Storage)
SMC-8 Case
Electrical Characteristics
Characteristic
Sym
Notes
Minimum
Typical
Maximum
Units
f
Output Frequency
Absolute Frequency
749.812
750.188
MHz
ppm
O
1, 2
Df
Tolerance from 700.000 MHz
Voltage into 50W (VSWR £ 1.2)
Operating Load VSWR
Symmetry
±250
O
V
Q and Q Output
0.60
49
.85
O
V
1, 3
P-P
2:1
51
3, 4, 5
3, 4, 6
%
Harmonic Spurious
-25
15
-20
-60
30
dBc
dBc
Nonharmonic Spurious
No Noise on V
ps
Q and Q Period Jitter
Output (Disabled)
3, 4, 6, 7
3, 4, 7, 8
3, 9
CC
P-P
200 mV
from 1 MHz to 1/2 f on
ps
35
P-P
O
P-P
mV
Amplitude into 50 W
75
P-P
3
50
KW
V
Output DC Resistance (between Q & Q)
V
V
-0.1
V
V
+0.1
CC
ENABLE (Terminal 14)
Input HIGH Voltage
IH
CC
CC
V
Input LOW Voltage
Input HIGH Current
Input LOW Current
Propagation Delay
Operating Voltage
Operating Current
0.0
0.20
5
V
IL
I
3, 9
3
mA
mA
ms
VDC
mA
°C
IH
I
-1
IL
t
1
PD
V
DC Power Supply
+3.13
0
+3.30
20
+3.47
40
CC
1, 3
1, 3
I
CC
T
Operating Ambient Temperature
+70
A
Lid Symbolization (YY = Year, WW = Week)
RFM SC3053B YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
Unless otherwise noted, all specifications include any combination of load 6.
VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 W loads to
ground. (See: Typical Test Circuit.)
Jitter and other spurious outputs induced by externally generated electrical noise
on VCC or mechanical vibration are not included. Dedicated external voltage
regulation and careful PCB layout are recommended for optimum performance.
Applies to period jitter of Q and Q. Measurements are made with the Tektronix
CSA803 signal analyzer with at least 1000 samples.
Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half
of fO at the VCC power supply terminal.
The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is
defined as the time from the 50% point on the rising edge of ENABLE to the 90%
point on the rising edge of the output amplitude or as the fall time from the 50%
point to the 10% point. (SEE: Timing Definitions.)
2.
3.
4.
5.
One or more of the following United States patents apply: 4,616,197; 4,670,681;
4,760,352.
7.
The design, manufacturing process, and specifications of this device are subject
to change without notice.
8.
Only under the nominal conditions of 50 W load impedance with VSWR £ 1.2 and
nominal power supply voltage.
9.
Symmetry is defined as the pulse width (in percent of total period) measured at
the 50% points of Q or Q. (See: Timing Definitions.)
RF Monolithics, Inc.
RFM Europe
Phone: (972) 233-2903
Phone: 44 1963 251383
Fax: (972) 387-9148
Fax: 44 1963 251510
E-mail: info@rfm.com
http://www.rfm.com
SC3053B-071201
Page 1 of 2
©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.
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