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SC16C650AIA44,529

更新时间: 2024-02-21 05:08:37
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟数据传输PC外围集成电路
页数 文件大小 规格书
50页 240K
描述
SC16C650AIA44

SC16C650AIA44,529 技术参数

生命周期:Obsolete零件包装代码:LPCC
包装说明:QCCJ,针数:44
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.76其他特性:ALSO OPERATES AT 2.5V MINIMUM SUPPLY
地址总线宽度:3边界扫描:NO
最大时钟频率:48 MHz通信协议:ASYNC, BIT
最大数据传输速率:0.375 MBps外部数据总线宽度:8
JESD-30 代码:S-PQCC-J44长度:16.585 mm
低功率模式:YES串行 I/O 数:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:16.585 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

SC16C650AIA44,529 数据手册

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SC16C650A  
UART with 32-byte FIFO and IrDA encoder/decoder  
Philips Semiconductors  
D0  
D1  
1
2
3
4
5
6
7
8
9
40 V  
CC  
39 RI  
D2  
38 DCD  
37 DSR  
36 CTS  
35 RESET  
34 OUT1  
33 DTR  
32 RTS  
31 OUT2  
30 INT  
D3  
D4  
D5  
D6  
D7  
RCLK  
RX 10  
TX 11  
CS0 12  
29 RXRDY  
28 A0  
CS1 13  
CS2 14  
27 A1  
BAUDOUT 15  
XTAL1 16  
XTAL2 17  
IOW 18  
26 A2  
25 AS  
24 TXRDY  
23 DDIS  
22 IOR  
21 IOR  
IOW 19  
GND 20  
002aaa299  
Fig 4. DIP40 pin configuration.  
5.2 Pin description  
Table 2:  
Symbol  
Pin description  
Pin  
Type Description  
PLCC44 LQFP48 DIP40  
A0-A2  
AS  
28, 27,  
26  
28, 27,  
26  
28, 27, I  
26  
Register select. A0-A2 are used during read and write operations to  
select the UART register to read from or write to. Refer to Table 3 for  
register addresses and refer to AS description.  
28  
24  
25  
I
Address strobe. When AS is active (LOW), A0, A1, and A2 and CS0,  
CS1, and CS2 drive the internal select logic directly; when AS is  
HIGH, the register select and chip select signals are held at the logic  
levels they were in when the LOW-to-HIGH transition of AS occurred.  
BAUDOUT  
17  
12  
15  
O
Baud out. BAUDOUT is a 16× clock signal for the transmitter section  
of the UART. The clock rate is established by the reference oscillator  
frequency divided by a divisor specified in the baud generator divisor  
latches. BAUDOUT may also be used for the receiver section by tying  
this output to RCLK.  
9397 750 11622  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 04 — 20 June 2003  
6 of 50  
 
 

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