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SC102205

更新时间： 2024-02-27 17:14:35
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
142页 6530K
描述
nullDevice User Guide

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SC102205 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：LQFP,针数：112
Reach Compliance Code：unknownECCN代码：3A001.A.3
HTS代码：8542.31.00.01风险等级：5.78
具有ADC：YES其他特性：ALSO REQUIRES 5V SUPPLY
地址总线宽度：20位大小：16
最大时钟频率：50 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：16
JESD-30 代码：S-PQFP-G112长度：20 mm
I/O 线路数量：91端子数量：112
最高工作温度：105 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE认证状态：Not Qualified
ROM可编程性：FLASH座面最大高度：1.6 mm
速度：25 MHz最大供电电压：2.75 V
最小供电电压：2.35 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：20 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

SC102205 数据手册

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Device User Guide — 9S12DT128DGV2/D V02.15  
Version Revision Effective  
Author  
Description of Changes  
Number  
Date  
Date  
Added 3L40K mask set in section 1.6  
Corrected register entries in section 1.5.1 “Detailed Memory Map”  
Updated description for ROMCTL in section 2.3.31  
Updated section 4.3.3 “Unsecuring the Microcontroller”  
Corrected and updated device-specific information for OSC  
(section 8.1) & Byteflight (section 15.1)  
29 Jan  
2003  
29 Jan  
2003  
V02.07  
Updated footnote in Table A-4 “Operating Conditions”  
Changed reference of VDDM to VDDR in section A.1.8  
Removed footnote on input leakage current in Table A-6 “5V I/O  
Characteristics”  
Added part numbers MC9S12DT128E, MC9S12DG128E, and  
MC9S12DJ128E in “Preface” and related part number references  
Removed mask sets 0L40K and 2L40K from Table 1-3  
26 Feb  
2003  
26 Feb  
2003  
V02.08  
Replaced references to HCS12 Core Guide by the individual  
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;  
updated Fig.3-1 “Clock Connections” to show the individual HCS12  
blocks  
Corrected PIM module name and document order number in Table  
0-2 “Document References”  
Corrected ECT pulse accumulators description in section 1.2  
“Features”  
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments  
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in  
Table 2.1 “Signal Properties”  
Mentioned “S12LRAE” bootloader in Flash section 17  
Corrected footnote on clamp of TEST pin under Table A-1  
“Absolute Maximum Ratings”  
15 Oct  
2003  
15 Oct  
2003  
V02.09  
Corrected minimum bus frequency to 0.25MHz in Table A-4  
“Operating Conditions”  
Replaced “burst programming” by “row programming” in A.3 “NVM,  
Flash and EEPROM”  
Corrected blank check time for EEPROM in Table A-11 “NVM  
Timing Characteristics”  
Corrected operating frequency in Table A-18 “SPI Master/Slave  
Mode Timing Characteristics  
Added A128 information in “Derivative Differences”, 2.1 “Device  
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4  
Added lead-free package option (PVE) in Table 0-2 “Derivative  
Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber  
Example”  
6 Feb  
2004  
6 Feb  
2004  
V02.10  
V02.11  
Added an “AEC qualified” row in the “Derivative Differences” tables  
0-1 & 0-2.  
Added part numbers SC515846, SC515847, SC515848, and  
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,  
and section 23.  
Corrected and added maskset 4L40K in tables 0-1 & 0-2 and  
section 1.6.  
3 May  
2004  
3 May  
2004  
Corrected BDLC module availability in DB128 80QFP part in  
“Derivative Differences” table 0-2.  
Freescale Semiconductor  
4
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