Datasheet > SC102204MFU

SC102204MFU

更新时间： 2024-01-21 12:21:25

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
142页	6530K
描述
16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP80

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SC102204MFU 数据手册

Device User Guide — 9S12DT128DGV2/D V02.15

Description of Changes

Version Revision Effective

Author

Number

Date

Changed XCLKS to PE7 in Table 2-2

Updated device part numbers in Figure 2-1

Updated BDM clock in Figure 3-1

Removed SIM description in overview & n_UPOSCspec in Table A-15

08 Mar

2002

08 Mar

2002

V02.02

Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH

(Table A-6), C_INS(Table A-9), C_IN(Table A-6 & A-15),

Updated interrupt pulse timing variables in Table A-6

Updated device part numbers in Figure 2-1

Added document numbers on cover page and Table 0-2

Cleaned up Fig. 1-1, 2-1

Updated Section 1.5 descriptions

Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.

Corrected NVM sizes in Sections 16, 17

Added I_REFspec for 1ATD in Table A-8

14 Mar

2002

14 Mar

2002

V02.03

Added Blank Check in A.3.1.5 and Table A-11

Updated CRG spec in Table A-15

Added:

Pull-up columns to signal table,

Example for PLL Filter calculation,

Thermal values for junction to board and package,

BGND pin pull-up

Part Order Information

Global Register Table

Chip Conﬁguration Summary

Device speciﬁc info on CRG

Modiﬁed:

16 Aug

2002

16 Aug

2002

V02.04

Reduced Wait and Run IDD values

Mode of Operation chapter

Changed leakage current for ADC inputs down to +-1uA

Minor modiﬁcation of PLL frequency/ voltage gain values

Corrected:

Pin names/functions on 80 pin packages

Interrupt vector table enable register inconsistencies

PCB layout for 80QFP VREGEN position

12 Sep

2002

12 Sep

2002

Corrected:

V02.05

V02.06

Removed document order no. from Revision History pages

Renamed "Preface" section to "Derivative Differences and

Document references". Added details for derivatives missing

CAN0/1/4, BDLC, IIC and/or Byteﬂight

Added 2L40K mask set in section 1.6

Added OSC User Guide in Preface, “Document References”

Added oscillator clock connection to BDM in S12_CORE in ﬁg 3-1

Corrected several register and bit names in “Local Enable” column

of Table 5.1 Interrupt Vector Locations

06 Nov

2002

06 Nov

2002

Section HCS12 Core Block Description: mentioned alternate clock

of BDM to be equivalent to oscillator clock

Added new section: “Oscillator (OSC) Block Description”

Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz

Freescale Semiconductor

1 234 5 6 7...142

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