1 Gb (128 MB) Dual-Quad FL-S Flash SPI Multi-I/O, 3.0 V
Signal descriptions
3.2
Multiple Input / Output (Dual-Quad SPI)
Quad input / output (I/O) commands send instructions to the memory only on the IO0 (Quad SPI-1) and IO4 (Quad
SPI-2) signals. Address is sent from the host to the memory as four bit (nibble) on IO0, IO1, IO2, IO3 (Quad
SPI-1)and repeated on IO4, IO5, IO6, IO7 (Quad SPI-2). Data is sent and returned to the host as bytes on IO0–IO7.
3.3
RESET#
The RESET# input provides a hardware method of resetting the device to standby state, ready for receiving a
command. When RESET# is driven to logic LOW (VIL) for at least a period of tRP, the device:
• terminates any operation in progress,
• tristates all outputs,
• resets the volatile bits in the Configuration Register,
• resets the volatile bits in the Status Registers,
• resets the Bank Address Register to zero,
• loads the Program Buffer with all ones,
• reloads all internal configuration information necessary to bring the device to standby mode,
• and resets the internal control unit to standby state.
RESET# causes the same initialization process as is performed when power comes up and requires tPU time.
RESET# may be asserted LOW at any time. To ensure data integrity any operation that was interrupted by a
hardware reset should be reinitiated once the device is ready to accept a command sequence.
When RESET# is first asserted LOW, the device draws ICC1 (50 MHz value) during tPU. If RESET# continues to be
held at VSS the device draws CMOS standby current (ISB).
RESET# has an internal pull-up resistor and may be left unconnected in the host system if not used.
The RESET# input is not available on all packages options. When not available the RESET# input of the device is
tied to the inactive state, inside the package.
3.4
Serial Clock (SCK1, SCK2)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in SDR
commands, and after every edge in DDR commands.
3.5
Chip Select (CS1#, CS2#)
The chip select signal indicates when a command for the device is in process and the other signals are relevant
for the memory device. When the CS# signal is at the logic HIGH state, the device is not selected and all input
signals are ignored and all output signals are high impedance. Unless an internal program, erase or write registers
(WRR) embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input
to logic LOW state enables the device, placing it in the Active Power mode. After power-up, a falling edge on CS#
is required prior to the start of any command.
3.6
Input Output IO0–IO7
These signals are input and outputs for receiving instructions, addresses, and data to be programmed (values
latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK, in SDR
commands, and on every edge of SCK, in DDR commands).
3.7
Core Voltage Supply (VCC)
VCC is the voltage source for all device internal logic. It is the single voltage used for all device internal functions
including read, program, and erase. The voltage may vary from 2.7 V to 3.6 V.
Datasheet
8
002-00466 Rev. *H
2022-07-19
5秒后页面跳转
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
