S7987-01

更新时间： 2024-02-28 21:41:34

品牌	Logo	应用领域
HAMAMATSU		传感器换能器图像传感器电视
页数	文件大小	规格书
7页	909K
描述
CCD area image sensor Back-thinned FT-CCD for low-light-level NTSC B/W TV application

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技术参数
数据手册

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S7987-01 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
风险等级：	5.76	Base Number Matches：	1

S7987-01 数据手册

CCD area image sensor S7986-01, S7987-01

Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)

ꢀꢀ

Parameter

Saturation output voltage

Vertical

Horizontal

CCD node sensitivity

Symbol

Vsat

Remark

Min.

Typ.

Fw × Sv

Max.

Unit

1.5

Full well capacity

130

2.0

µV/e

25 °C

0 °C

2,000

100

6,000

300

Dark current

(MPP mode)

e /pixel/s

Readout noise

150

e rms

Dynamic range (area scanning)

Spectral response range

100

430

200 to 1,100

Photo response non-uniformity

*4: VOD=15 V, Load resistance=2.2 kΩ

PRNU

+/-10

*5: Dark current doubles for every 5 to 7 °C.

*6: -40 °C, operating frequency is 12 MHz.

*7: DR = Fw / Nr

*8: Measured at half of the full well capacity.

PRNU (%) = noise / signal × 100

Noise: fixed pattern noise (peak to peak)

Pin connections

ꢀꢀ

S7986-01

Description

Reset drain

Output transistor source

Output transistor drain

Output gate

S7987-01

Description

Reset drain

Output transistor source

Output transistor drain

Output gate

No.

Remark

Symbol

Summing gate

Same timing as P2H

P2H

P1H

P2H

P1H

CCD horizontal register clock-2

CCD horizontal register clock-1

CCD horizontal register clock-2

CCD horizontal register clock-1

IG2H Test point (horizontal input gate-2)

IG1H Test point (horizontal input gate-1)

IG2H Test point (horizontal input gate-2)

IG1H Test point (horizontal input gate-1)

Shorted to 0 V

ISH

Test point (horizontal input source)

Transfer gate

Test point (horizontal input source)

Transfer gate

Shorted to RD

Same timing as P2VS ^*9

CCD vertical register clock-2

(storage area)

CCD vertical register clock-1

(storage area)

CCD vertical register clock-2

(storage area)

CCD vertical register clock-1

(storage area)

P2VS

P1VS

P2VS

P1VS

Th1

Th2

P-

Thermistor

TE-cooler-

TE-cooler+

Substrate (GND)

CCD vertical register clock-2

(image area)

CCD vertical register clock-1

(image area)

P+

Substrate (GND)

CCD vertical register clock-2

(image area)

CCD vertical register clock-1

(image area)

P2VI

P1VI

P2VI

P1VI

Reset gate

*9: TG is an isolation gate between vertical register and horizontal resister.

In standard operation, the same pulse of P2VS should be applied to the TG.

1 234 5 6 7

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