Datasheet > S5T8701

S5T8701

更新时间： 2022-11-26 04:34:46

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S5T8701 数据手册

S5T8701

FLEX ^TMROAMING DECODER II

SPI PACKETS

All data communicated between the S5T8701 and the host MCU is transmitted on the SPI in 32-bit packets. Each

packet consists of an 8-bit ID followed by 24 bits of information. The S5T8701 uses the SPI bus in full duplex

mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data.

The SPI interface consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO). The SS is used as a

chip select for the S5T8701. The SCK is a clock supplied by the host MCU. The data from the host is transmitted

on the MOSI(Master-Out-Slave-In) line. The data from the S5T8701 is transmitted on the MISO(Master-In-Slave-

Out) line.

Timing requirements for SPI communication are specified in "SPI Timing" on page 69.

Packet Communication Initiated by the Host

Refer to figure 6 on page 11. When the host sends a packet to the S5T8701, it performs the following steps:

Select the S5T8701 by driving the SS pin low.

Wait for the S5T8701 to drive the READY pin low.

Send the 32-bit packet.

De-select the S5T8701 by driving the SS pin high.

Repeat steps 1 through 4 for each additional packet.

READY

SCK

MOSI

MISO

D31

D1 D0

D31

D1 D0

D31

D1 D0

High-impedance State

Figure 6: Typical Multiple Packet Communications Initiated by the Host

When the host sends a packet, it will also receive a valid packet from the S5T8701. If the S5T8701 is enabled

(see "Checksum Packet" on page 16 for a definition of enabled) and has no other packets waiting to be sent, the

S5T8701 will send a status packet.

The host must transition the SS pin from high to low to begin each 32-bit packet. The S5T8701 must see a

negative transition on the SS pin in order for the host to initiate each packet communication.

1...5 6 789 10 11...70

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