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S29PL127J55BFW020 PDF预览

S29PL127J55BFW020

更新时间: 2023-07-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
114页 1040K
描述
Flash, 8MX16, 55ns, PBGA64, 8 X 11.60 MM, LEAD FREE, FBGA-64

S29PL127J55BFW020 数据手册

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P r e l i m i n a r y  
Page Mode Features  
The page size is 8 words. After initial page access is accomplished, the page mode  
operation provides fast read access speed of random locations within that page.  
Standard Flash Memory Features  
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both  
read and write functions. Internally generated and regulated voltages are pro-  
vided for the program and erase operations.  
The device is entirely command set compatible with the JEDEC 42.4 sin-  
gle-power-supply Flash standard. Commands are written to the command  
register using standard microprocessor write timing. Register contents serve as  
inputs to an internal state-machine that controls the erase and programming cir-  
cuitry. Write cycles also internally latch addresses and data needed for the  
programming and erase operations. Reading data out of the device is similar to  
reading from other Flash or EPROM devices.  
Device programming occurs by executing the program command sequence. The  
Unlock Bypass mode facilitates faster programming times by requiring only two  
write cycles to program data instead of four. Device erasure occurs by executing  
the erase command sequence.  
The host system can detect whether a program or erase operation is complete by  
reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program  
or erase cycle has been completed, the device is ready to read array data or ac-  
cept another command.  
The sector erase architecture allows memory sectors to be erased and repro-  
grammed without affecting the data contents of other sectors. The device is fully  
erased when shipped from the factory.  
Hardware data protection measures include a low VCC detector that automat-  
ically inhibits write operations during power transitions. The hardware sector  
protection feature disables both program and erase operations in any combina-  
tion of sectors of memory. This can be achieved in-system or via programming  
equipment.  
The Erase Suspend/Erase Resume feature enables the user to put erase on  
hold for any period of time to read data from, or program data to, any sector that  
is not selected for erasure. True background erase can thus be achieved. If a read  
is needed from the Secured Silicon Sector area (One Time Program area) after  
an erase suspend, then the user must use the proper command sequence to  
enter and exit this region.  
The Program Suspend/Program Resume feature enables the user to hold the  
program operation to read data from any sector that is not selected for program-  
ming. If a read is needed from the Secured Silicon Sector area, Persistent  
Protection area, Dynamic Protection area, or the CFI area, after a program sus-  
pend, then the user must use the proper command sequence to enter and exit  
this region.  
The device offers two power-saving features. When addresses have been stable  
for a specified amount of time, the device enters the automatic sleep mode.  
The system can also place the device into the standby mode. Power consumption  
is greatly reduced in both these modes.  
The device electrically erases all bits within a sector simultaneously via  
Fowler-Nordheim tunneling. The data is programmed using hot electron injection.  
March 2, 2005 S29PL-J_00_A7  
S29PL-J  
5

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