RX621 PDF预览

RX621

更新时间: 2025-07-22 11:16:23
品牌 Logo 应用领域
瑞萨 - RENESAS 微控制器
页数 文件大小 规格书
146页 1021K
描述
32-bit Microcontroller with 100MHz High-speed Operation and Built-in Connectivity Functions such as Ethernet and USB Host

RX621 数据手册

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Features  
Datasheet  
RX62N/RX621 Group  
R01DS0052EJ0110  
Rev.1.10  
RENESAS 32-Bit MCU  
Feb 10, 2011  
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash,  
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,  
RTC, up to 14 communication channels  
Features  
32-bit RX CPU Core  
TFLGA85 7×7mm, 0.65mm pitch  
TFLGA145 9×9mm, 0.65mm pitch  
LFBGA176 13×13mm, 0.8mm pitch  
Delivers 165 DMIPS at a maximum operating frequency of  
100 MHz  
Single Precision 32-bit IEEE-754 Floating Point  
Accumulator: 32 × 32 to 64-bit result, one instruction  
Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for  
multiple instructions  
Interrupt response in as few as 5 CPU clock cycles  
CISC-Harvard Architecture with 5-stage pipeline  
Variable length instructions, ultra compact code  
Supports the Memory Protection Unit (MPU)  
Background JTAG debug plus high-speed trace  
LQFP100 14×14mm, 0.5mm pitch  
LQFP144 20×20mm, 0.5mm pitch  
Up to 14 Communication Interfaces  
(2) USB 2.0 Full-Speed interfaces with PHY  
Supports Host/Function/OTG  
10 endpoints for types: Control, Interrupt, Bulk, Isochronous  
(1) Ethernet MAC 10/100 Mbps, Half or Full Duplex  
Supported.  
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.  
RMII or MII interface to external PHY  
(1) CAN ISO11898-1, supports 32 mailboxes  
(6) SCI channels: Asynchronous, clock sync, smartcard,  
and 9-bit modes  
Low Power Design and Architecture  
2.7V to 3.6V operation from a single supply  
480 µA/MHz Run Mode with all peripherals on  
Deep Software Standby Mode with RTC  
Four low power modes  
Main Flash Memory, no Wait-State  
100 MHz operation, 10 nsec read cycle  
No wait states for read at full CPU speed  
256K, 384K, 512K Byte size options  
For Instructions or Operands  
(2) I2C interfaces up to 1M bps, SMBus support  
(2) RSPI  
Programming from USB, SCI, JTAG, user code  
External Address Space  
Data Flash Memory  
Eight CS areas (8 × 16 Mbytes)  
128-Mbyte SDRAM area  
8-/16-/32-bit bus space selectable for each area  
Up to 32K Bytes with 30K Erase Cycles  
Background Erase/Program does not stall CPU  
SRAM, no Wait-State  
TFT-LCD up to WQVGA resolution  
64K or 96K Byte size options  
For Operands or Instructions  
Back-up retention in Deep Software Standby Mode  
Up to 20 Extended Function Timers  
(12) 16-bit MTU2  
Input capture, Output Compare, PWM output, phase count  
mode  
DMA  
Four fully programmable internal DMA channels  
Two EXDMA channels for external-to-external transfers  
Data Transfer Controller (DTC)  
(4) 8-bit TMR  
(4) 16-bit CMT  
1-MHz ADC units with two combination choices  
Reset and Supply Management  
12-bit × 8 ch. unit with single sample/hold circuit  
Power-On Reset (POR) monitor/generator  
Low Voltage Detect (LVD) with precision setting  
or (2) 10-bit × 4 ch units each with a sample/hold circuit  
AD-converted value addition mode (12-bit A/D converter)  
System Clocking with Clock Monitoring  
10-bit DAC, 2 channels  
External crystal, 8 MHz to 14 MHz to Internal PLL  
PLL source to system, USB, and Ethernet  
Internal 125 kHz LOCO for IWDT  
Up to 128 GPIO  
5V tolerant, Open-Drain, Internal Pull-up  
External crystal, 32 kHz for RTC  
Operation Temp  
Real Time Clock  
Full calendar function, BCD format  
–40°C to +85°C  
Two Independent Watchdog Timers  
125-kHz LOCO operation  
R01DS0052EJ0110 Rev.1.10  
Feb 10, 2011  
Page 1 of 146  

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