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RTQ2536-QA PDF预览

RTQ2536-QA

更新时间: 2024-02-16 20:18:26
品牌 Logo 应用领域
立锜 - RICHTEK 双倍数据速率
页数 文件大小 规格书
11页 206K
描述
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RTQ2536-QA 技术参数

Status:ActiveMemory Supported:DDRI;DDRII;DDRIII;DDRIV
Vin (min) (V):1Vin (max) (V):3.5
VTT Output Tolerance (max) (+/- mV):30Isource/Isink (max) (A):2
Standby Current (typ) (mA):0.5Current Limit (typ) (A):2
Features:Enable Input;OCP;Stable with Ceramic CapacitorPackage Type:WDFN3x3-10S

RTQ2536-QA 数据手册

 浏览型号RTQ2536-QA的Datasheet PDF文件第1页浏览型号RTQ2536-QA的Datasheet PDF文件第2页浏览型号RTQ2536-QA的Datasheet PDF文件第4页浏览型号RTQ2536-QA的Datasheet PDF文件第5页浏览型号RTQ2536-QA的Datasheet PDF文件第6页浏览型号RTQ2536-QA的Datasheet PDF文件第7页 
RTQ2536-QA  
Functional Block Diagram  
REFOUT  
VIN  
S3  
S5  
OTP  
+
OCP  
-
VCNTL  
UVLO  
EN_VTT  
VOUT  
PGND  
VDDQSNS  
+
-
+
-
+
OCP  
-
SENSE  
GND  
Operation  
The RTQ2536-QAis a linear sink/sourceDDR termination  
regulator with current capability up to 2A. The RTQ2536-  
QAbuilds in a high-sideN-MOSFET which provides current  
sourcing and a low-sideN-MOSFET which provides current  
sinking. All the control circuits are supplied by the power  
VCNTL. In normal operation, the error amplifier OP adjusts  
the gate driving voltage of the power MOSFET to achieve  
SENSE voltage well tracking the VDDQSNS/2 voltage.  
Thermal Protection  
Both the high-side and low-side power MOSFETs will be  
turned off when the junction temperature is higher than  
typically 160°C, and be released to normal operation when  
junction temperature falls below 135°C typically.  
Power State Control  
The input pins S3 and S5 of the RTQ2536-QA, provide  
simple control of the power state. Table 1 describes S3/  
S5 terminal logic state and corresponding state of  
REFOUT/VOUT outputs. VOUT is turn-off and discharged  
to GND in state S3. When both S5 and S3 pins are LOW,  
the power state is set to S4/S5. In S4/S5 state, all the  
outputs are turn-off and discharged toGND.  
Both the source and sink currents are detected by the  
internal sensing resistor, and the OCP function will work  
to limit the current to a designed value when overload  
happens. Furthermore, the current will be folded back to  
be one half if VOUT is out of the power good window.  
Buffer  
This function provides REFOUT output equal to  
VDDQSNS/2 with 10mA source/sink current capability.  
Control Logic  
This block includes VCNTL UVLO, VDDQSNS UVLO and  
Enable/Disable functions, and provides logic control to  
the whole chip.  
Table 1. S3 and S5 Control Table  
STATE  
S0  
S3  
HI  
S5  
HI  
REFOUT  
ON  
VOUT  
ON  
S3  
LO  
LO  
HI  
ON  
OFF (Discharge)  
S4/S5  
LO  
OFF (Discharge) OFF (Discharge)  
Copyright 2018 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DSQ2536-QA-01 September 2018  
www.richtek.com  
3

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