RTL8110SB(L)
Datasheet
List of Figures
FIGURE 1. 128-PIN (L)QFP PIN ASSIGNMENTS ............................................................................................................................3
FIGURE 2. LITTLE-ENDIAN BYTE ORDERING..............................................................................................................................10
FIGURE 3. BIG-ENDIAN BYTE ORDERING...................................................................................................................................11
FIGURE 4. TARGET READ OPERATION........................................................................................................................................12
FIGURE 5. TARGET WRITE OPERATION ......................................................................................................................................13
FIGURE 6. MASTER READ OPERATION .......................................................................................................................................14
FIGURE 7. MASTER WRITE OPERATION......................................................................................................................................15
FIGURE 8. RX LED.....................................................................................................................................................................17
FIGURE 9. TX LED.....................................................................................................................................................................18
FIGURE 10. TX/RX LED ..............................................................................................................................................................19
FIGURE 11. LINK/ACT LED ......................................................................................................................................................20
FIGURE 12. SERIAL EEPROM INTERFACE TIMING......................................................................................................................28
FIGURE 13. OUTPUT TIMING MEASUREMENT CONDITIONS .........................................................................................................30
FIGURE 14. INPUT TIMING MEASUREMENT CONDITIONS.............................................................................................................30
FIGURE 15. 3.3V CLOCK WAVEFORM .........................................................................................................................................31
FIGURE 16. CLOCK SKEW DIAGRAM ...........................................................................................................................................31
FIGURE 17. I/O READ ..................................................................................................................................................................32
FIGURE 18. I/O WRITE.................................................................................................................................................................32
FIGURE 19. CONFIGURATION READ.............................................................................................................................................33
FIGURE 20. CONFIGURATION WRITE ...........................................................................................................................................33
FIGURE 21. BUS ARBITRATION....................................................................................................................................................34
FIGURE 22. MEMORY READ BELOW 4GB....................................................................................................................................34
FIGURE 23. MEMORY WRITE BELOW 4GB..................................................................................................................................35
FIGURE 24. TARGET INITIATED TERMINATION - DISCONNECT.....................................................................................................35
FIGURE 25. TARGET INITIATED TERMINATION - ABORT..............................................................................................................36
FIGURE 26. MASTER INITIATED TERMINATION - ABORT .............................................................................................................36
FIGURE 27. PARITY OPERATION – ONE EXAMPLE .......................................................................................................................37
FIGURE 28. MEMORY READ ABOVE 4GB (DAC)........................................................................................................................38
FIGURE 29. MEMORY WRITE ABOVE 4GB (DAC) ......................................................................................................................38
Integrated Gigabit Ethernet Controller (LOM)
vi
Track ID: JATR-1076-21 Rev. 1.6
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