RT9625A
Application Information
The RT9625A is a high frequency, two-channel
synchronous rectified MOSFET driver containing Richtek's
advanced MOSFET driver technologies. The RT9625Ais
designed to be able to adapt from normal MOSFET driving
applications to high performance CPU VR driving
capabilities.
The PWMx signal is acted as “ High” if the signal is above
the rising threshold and acted as “Low” if the signal is
below the falling threshold. When PWM signal level enters
and remains within the shutdown window, the output drivers
are disabled and both MOSFET gates are pulled and held
low. If the PWMx signal is left floating, the pin will be kept
around 1.8V by the internal divider and provide the PWMx
controller with a recognizable level.
Supply Voltage and Power On Reset
The RT9625Acan be utilized under both VCC = 5V or VCC
= 12V applications which may happen in different fields of
electronics application circuits. In terms of efficiency,
higher VCC equals higher driving voltage of UGATEx/
LGATEx which may result in higher switching loss and
lower conduction loss of power MOSFETs. The choice of
VCC = 12V or VCC = 5V can be a tradeoff to optimize
system efficiency.
Bootstrap Power Switch
The RT9625Abuilds in internal bootstrap power switches
to replace external bootstrap diode, and this can facilitate
PCB design and reduce total BOM cost of the system.
Hence, no external bootstrap diode is required in real
applications.
Non-overlap Control
The RT9625A controls both high side and low side N-
MOSFETs of two half-bridge power according to two
external input PWMx control signals. It has Power On
Reset (POR) function which held UGATEx and LGATEx
low before the VCC voltage rises to higher than rising
threshold voltage. When VCC exceeds the POR threshold
voltage, the voltage at the POR pin will be pulled high.
To prevent the overlap of the gate drivers during the
UGATEx pull low and the LGATEx pull high, the non-overlap
circuit monitors the voltages at the PHASEx node and
high side gate drive (UGATEx − PHASEx). When the
PWMx input signal goes low, UGATEx begins to pull low
(after propagation delay). Before LGATEx is pulled high,
the non-overlap protection circuit ensures that the
monitored voltages have gone below 1.1V. Once the
monitored voltages fall below 1.1V, LGATEx begins to turn
high. By waiting for the voltages of the PHASEx pin and
high side gate driver to fall below 1.1V, the non-overlap
protection circuit ensures that UGATEx is low before
LGATEx pulls high.
Enable and Disable
The RT9625A includes an ENx pin for sequence control.
When the ENx pin rises above the VENH trip point, the
RT9625Abegins a new initialization and follows the PWMx
command to control the UGATEx and LGATEx. When the
ENx pin falls below the VENL trip point, the RT9625A shuts
down and keeps UGATEx and LGATEx low.
Also to prevent the overlap of the gate drivers during
LGATEx pull low and UGATEx pull high, the non-overlap
circuit monitors the LGATEx voltage. When LGATEx goes
below 1.1V, UGATEx goes high after propagation delay.
Tri-state PWM Input
After the initialization, the PWMx signal takes the control.
The rising PWMx signal first forces the LGATEx signal to
turn low then UGATEx signal is allowed to go high just
after a non-overlapping time to avoid shoot through current.
The falling of PWMx signal first forces UGATEx to go low.
When UGATEx and PHASEx signal reach a
predetermined low level, LGATEx signal is allowed to turn
high.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the
gate draws the current only for few nano-amperes. Thus
once the gate has been driven up to “ON” level, the
current could be negligible.
Copyright 2015 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
10
DS9625A-04 July 2015
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
