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RT100KP180AE3TR

更新时间： 2024-02-26 08:24:03
品牌 Logo 应用领域
美高森美 - MICROSEMI 局域网二极管电视
页数 文件大小 规格书
5页 260K
描述
100000W, UNIDIRECTIONAL, SILICON, TVS DIODE, ROHS COMPLIANT, PLASTIC, CASE 5A, 2 PIN

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RT100KP180AE3TR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：O-PALF-W2
针数：2Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.10.00.50
风险等级：5.73其他特性：HIGH RELIABILITY
最大击穿电压：221 V最小击穿电压：200 V
击穿电压标称值：210.5 V外壳连接：ISOLATED
最大钳位电压：291 V配置：SINGLE
二极管元件材料：SILICON二极管类型：TRANS VOLTAGE SUPPRESSOR DIODE
JESD-30 代码：O-PALF-W2JESD-609代码：e3
湿度敏感等级：1最大非重复峰值反向功率耗散：100000 W
元件数量：1端子数量：2
封装主体材料：PLASTIC/EPOXY封装形状：ROUND
封装形式：LONG FORM峰值回流温度（摄氏度）：NOT SPECIFIED
极性：UNIDIRECTIONAL最大功率耗散：1.61 W
认证状态：Not Qualified最大重复峰值反向电压：180 V
子类别：Transient Suppressors表面贴装：NO
技术：AVALANCHE端子面层：MATTE TIN
端子形式：WIRE端子位置：AXIAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

RT100KP180AE3TR 数据手册

 浏览型号RT100KP180AE3TR的Datasheet PDF文件第1页浏览型号RT100KP180AE3TR的Datasheet PDF文件第2页浏览型号RT100KP180AE3TR的Datasheet PDF文件第3页浏览型号RT100KP180AE3TR的Datasheet PDF文件第5页 
TECHNICAL DATA SHEET  
Gort Road Business Park, Ennis, Co. Clare, Ireland.  
Tel: +353 (0) 65 6840044, Fax: +353 (0) 65 6822298  
6 Lake Street, Lawrence, MA 01841  
Tel: 1-800-446-1158 / (978) 794-1666, Fax: (978) 6890803  
Website: http://www.microsemi.com  
___________________________________________________________________________________________________________________________________  
GRAPHS  
tp – Pulse Time – sec.  
TL Lead Temperature oC  
FIGURE 1  
Peak Pulse Power vs. Pulse Time  
To 50% of Exponentially Decaying Pulse  
FIGURE 2  
POWER DERATING  
NOTE: This PPP versus time graph allows the designer to use these parts over a broad  
power spectrum using the guidelines illustrated in MicroNote 104 on  
www.microsemi.com. Aircraft transients are described with exponential decaying  
waveforms. For suppression of square-wave impulses, derate power and current to  
66% of that for exponential decay shown in Figure 1.  
INSTALLATION  
Correct  
Incorrect  
TVS devices used across power lines are  
subject to relatively high magnitude surge  
currents and are more prone to adverse  
parasitic inductance effects in the  
mounting leads. Minimizing the shunt  
path of the lead inductance and their  
V = -Ldi/dt effects will optimize the TVS  
effectiveness.  
Examples of optimum  
installation and poor installation are  
illustrated in Figures 3 to 6. Figure 3  
illustrates minimal parasitic inductance  
with attachment at end of device.  
Inductive voltage drop is across input  
leads. Virtually no “overshoot” voltage  
results as illustrated with Figure 4. The  
loss of effectiveness in protection caused  
by excessive parasitic inductance is  
illustrated in Figures 5 and 6. Also see  
MicroNote 111 for further information on  
“Parasitic Lead Inductance in TVS”.  
FIGURE 3  
FIGURE 5  
FIGURE 4  
FIGURE 6  
RF01012 Rev A, August 2010  
High Reliability Product Group  
Page 4 of 5  
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