RL78/H1D
1.3
1. OUTLINE
Pin Configuration (Top View)
80-pin products (R5F11NM)
1.3.1
• 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P70/SEG8
P11/SEG30
P12/SEG31
P13/SEG32
P14/SEG33
P15/SEG34
P16/SEG35
P17/(TI07/TO07)
P84/(TI05/TO05)
P85/INTP7
P86/(INTP6)
ANI12
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P71/SEG9
P72/SEG10
P73/SEG11
P74/SEG12
P75/SEG13
P76/SEG14
P77/TI07/TO07/SEG15
P30/INTP3/RTC1HZ/SEG16
P31/TI01/TO01/SEG17
RL78/H1D
(Top View)
P32/INTP4/SSI00/SEG18
P35/SCK00/SCL00/SEG19
P36/SI00/RxD0/TOOLRxD/SDA00/PCLBUZ1/SEG20
ANI13
ANI14
P37/SO00/TxD0/TOOLTxD/SEG21
AVSS
P125/(TI06/TO06)/VL3
AMP0O
VL4
AMP0N/AMP0P
AMP0P
VL2
VL1
PGA00P
P126/(TI05/TO05)/CAPL
P127/(TI04/TO04)/CAPH
PGA00N
SBIAS
1
2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 µF).
Caution 2. Connect the REGA pin to AVSS pin via a capacitor (0.22 μF).
Caution 3. Make the AVSS pin the same potential as the VSS pin.
Caution 4. Make the AVDD pin the same potential as the VDD pin.
Caution 5. Connect the SBIAS pin to AVSS pin via a capacitor (0.22 µF).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection registers 0 to 3
(PIOR0 to PIOR3).
Remark 3. Set the AMP0P and AMP0N functions in the above figure by the amplifier unit 1 input select register (AMP0S).
R01DS0318EJ0110 Rev. 1.10
Apr 28, 2023
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