Introduction
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Introduction
The Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process is a follow
on to the Pentium 4 processor in the 478-pin package with Intel® NetBurst™
microarchitecture. The Pentium 4 processor with 512-KB L2 cache on 0.13 micron
process utilizes Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a
478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B
socket. The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process, like its
predecessor, the Pentium 4 processor in the 478-pin package, is based on the same Intel
32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software. In
this document, the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process
will be referred to as the “Pentium 4 processor with 512-KB L2 cache on 0.13 micron
process,” or simply “the processor.”
The Intel NetBurst microarchitecture features include hyper pipelined technology, a rapid
execution engine, a 400-MHz or a 533-MHz system bus, and an execution trace cache.
The hyper pipelined technology doubles the pipeline depth in the Pentium 4 processor
with 512-KB L2 cache on 0.13 micron process, allowing the processor to reach much
higher core frequencies. The rapid execution engine allows the two integer ALUs in the
processor to run at twice the core frequency, which allows many integer instructions to
execute in 1/2 clock tick. The 400-MHz or 533-MHz system bus is a quad-pumped bus
running off a 100-MHz or a 133-MHz system clock making 3.2 Gbytes/sec and
4.3 Gbytes/sec data transfer rates possible. The execution trace cache is a first-level
cache that stores approximately 12-k decoded micro-operations, which removes the
instruction decoding logic from the main execution path, thereby increasing performance.
Additional features within the Intel NetBurst microarchitecture include advanced dynamic
execution, advanced transfer cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves
speculative execution and branch prediction internal to the processor. The advanced
transfer cache is a 512 KB, on-die level 2 (L2) cache. A new floating point and multi media
unit has been implemented which provides superior performance for multi-media and
mathematically intensive applications. Finally, SSE2 adds 144 new instructions for
double-precision floating point, SIMD integer, and memory management. Power
management capabilities such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep have
been retained.
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech
recognition. The new packed double-precision floating-point instructions enhance
performance for applications that require greater range and precision, including scientific
and engineering applications and advanced 3-D geometry techniques, such as ray
tracing.
The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process Intel NetBurst
microarchitecture system bus utilizes a split-transaction, deferred reply protocol like the
Pentium 4 processor. This system bus is not compatible with the P6 processor family bus.
The Intel NetBurst microarchitecture system bus uses Source-Synchronous Transfer
(SST) of address and data to improve performance by transferring data four times per bus
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus
can deliver addresses two times per bus clock and is referred to as a “double-clocked” or
2X address bus. Working together, the 4X data bus and 2X address bus provide a data
bus bandwidth of up to 4.3 Gbytes/second.
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Datasheet