RDA Microelectronics, Inc.
RDA1846S Datasheet V0.1
Table 7-1
RDA1846S Pins Description
SYMBOL
PIN
1
DESCRIPTION
AVDD
SCLK
SDIO
Power supply
Clock input for serial control bus
2
3
Data input/output for serial control bus
Power supply
AVDD
XTAL1
XTAL2
4
5
Oscillator pin 1
6
Oscillator pin 2
Control Interface select
When MODE = VL, I2C Interface is select
When MODE = VH, SPI Interface is select
Latch enable (active low) input for serial control bus
Audio signal output to speaker
No connection
MODE
7
SENB
AFOUT
NC*
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
MIC_IN
Cc
MIC input
Compensation capacitor connection pin
Power supply
AVDD
NC*
No connection
RFIN
AVDD
NC*
RF signal input
Power supply
No connection
RFOUT
NC*
RF signal output
No connection
NC*
No connection
AVDD
PABIAS
AVDD
Power supply
PA bias supply for PA
Power supply
Chip enable, high active
Chip sleep , low active
Gpio7 / vox
PDN
24
25
26
27
28
GPIO7
GPIO6
GPIO5
GPIO4
(When Gpio7=VH, vox is active; else VL)
Gpio6 / sq
(When Gpio6=VH, sq is active; else VL)
Gpio5 / txon
(When Gpio5=VH, txon is active; else VL)
Gpio4 / rxon
(When Gpio4=VH, rxon is active; else VL)
Gpio3 / sdo
GPIO3
GPIO2
29
30
(Gpio3=VH or VL, it is the output register data in 4 wire control
interface mode)
Gpio2 / int
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
Page 9 of 16