Datasheet > RC19024

RC19024

更新时间： 2023-12-20 18:45:14

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
112页	2815K
描述
PCIe Gen6 24-Output Clock Buffer

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RC19024 数据手册

Datasheet

RC190xx

PCIe Gen5/6 Fanout Buffer Family with LOS

The RC190xx (RC19024, RC19020, RC19020A072,

RC19016, RC19013, RC19008, RC19004, and

RC19002) ultra-high performance fanout buffers

support PCIe Gen5 and Gen6. They provide a Loss-

Of-Signal (LOS) output for system monitoring and

redundancy. The devices also incorporate Power

Down Tolerant (PDT) and Flexible Startup

Features

▪ PCIe Gen5 additive phase jitter: 6fs RMS

▪ PCIe Gen6 additive phase jitter: 4fs RMS

▪ DB2000Q additive phase jitter: 10fs RMS

▪ 12kHz to 20MHz additive phase jitter: 30fs RMS at

156.25MHz

Sequencing (FSS) features, easing system design.

They can drive both source-terminated and double-

terminated loads, operating up to 400MHz.

▪ Power Down Tolerant (PDT) inputs

▪ Flexible Startup Sequencing (FSS)

▪ Automatic Clock Parking (ACP) upon loss of CLKIN

▪ Spread-spectrum tolerant

The family offers 2, 4, 8, 13, 16, 20, and 24 Low-

Power (LP) HCSL output pairs in 3 × 3 mm to

10 × 10 mm packages. The RC190xx devices offer

higher output counts in smaller packages compared

to earlier buffer families. The buffers support both

Common Clock (CC) and Independent Reference (IR)

PCIe clock architectures.

▪ CLKIN accepts HCSL or LVDS signal levels

▪ -40 to +105°C, 3.3V ±10% operation

▪ All devices except RC19002:

• Selectable output slew rate via pin/SMBus

• 4-wire Side-Band Interface supports high-speed

serial output enable and device daisy-chaining

Applications

▪ Cloud/High-performance computing

▪ nVME storage

• 9 SMBus addresses plus write protection

• 85Ω or 100Ω (A100 suffix) output impedance

• Pin-selectable slew rate

▪ Networking

▪ Accelerators

▪ RC19002: Pin-selectable output impedance

Clock Detect

LOSb

CLKb23

CLK23

CLKINb

CLKIN

Control Logic

SADR_tri[1:0]

SCLK

SMBus

Interface

Note 3

SDATA

or 2

outputs

PWRGD_PWRDNb

SLEWRATE_SEL

Note 1, 3

CLKb0

CLK0

Output Control

OEb[m:n]

SBI_IN

Note 2, 3

Note 3

SBI_CLK

SHFT_LDb

SBI_ENQ

Note 2, 3

Side-Band

Interface

SBI_OUT

1. RC19016/13/08/04 only. Other devices use SMBus.

2. Some devices mux SBI with OEb pins. See specific pinouts. Devices with SBI have dedicated SBI_ENQ pin.

3. Does not apply to the RC19002. On RC19002, the SLEWRATE_SEL pin is ZOUT_SEL.

Figure 1. RC190xx Block Diagram

R31DS0016EU0118 Rev.1.18

Nov 1, 2023

Page 1

12 3 4 5 6 7...112

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