Datasheet > RC19202

RC19202

更新时间： 2023-12-20 18:44:05

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
69页	1954K
描述
PCIe Gen6 2:2 Clock Multiplexer

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RC19202 数据手册

Datasheet

RC192xx

PCIe Gen5/6 2-Input Clock Mux Family with LOS

The RC192xx (RC19202, RC19204, RC19208,

RC19216) are ultra-high performance clock muxes

supporting PCIe Gen5 and Gen6. They provide a

Loss-Of-Signal (LOS) output for system monitoring

and redundancy. The devices also incorporate Power

Down Tolerance (PDT), Flexible Power Sequencing

(FPS), and Automatic Clock Parking (ACP) features

to insure good behavior under abnormal system

conditions. They can drive both source-terminated

and double-terminated loads up to 400MHz. The

CLKIN inputs also support either HCSL or LVDS

signaling levels, making the devices ideal for LVDS to

HCSL level translation. The excellent phase jitter and

PNSR performance make the RC192xx well suited for

network applications.

Features

▪ 2, 4, 8, or 16 Low-Power (LP) HCSL outputs saves

up to 64 resistors

▪ 2:N or 2 x 1:N/2 modes (N is number of outputs)

▪ 85Ω or 100Ω output impedance

▪ Outputs drive both source-terminated and double-

terminated loads

▪ Open-drain LOS output

▪ FPS allows inputs and clocks to be applied before

power is applied or power to be applied with no

input clock

▪ ACP cleanly parks outputs in low/low state when

selected input clock is lost

▪ Spread-spectrum tolerant

▪ Up to 8 output enable pins

Applications

▪ Cloud/High-performance Computing

▪ Selectable 4-wire Side-Band-Interface (SBI) for

hardware output enable (RC19208, RC19216)

▪ nVME Storage

▪ Networking

▪ SMBus write protection features (RC19216)

▪ Accelerators

▪ CLKIN pins directly support HCSL or LVDS

signaling levels

Key Specifications

▪ 3 × 3 mm 20-VFQFPN to 6 × 6 mm 80-GQFN

packages

▪ PCIe Gen5 additive phase jitter: 7fs RMS

▪ PCIe Gen6 additive phase jitter: 4fs RMS

▪ DB2000Q additive phase jitter: 9fs RMS

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ 12kHz-20MHz additive phase jitter: 37fs RMS at

156.25MHz

▪ Independent Reference (IR) with and without

spread spectrum

▪ 1MHz to 400MHz operation with ACP disabled

▪ 25MHz to 400MHz operation with ACP enabled

CLKb15

CLK15

CLKINb1

Bank 1

CLKIN1

CLKb8

CLK8

CLKSEL_tri

Bank 0

Clock

Detect

2, 4, or 16

outputs

CLKSEL_tri

LOSb

CLKIN0

CLKIN1

CLKIN0

CLKIN1

Bank 1

CLKb7

CLK7

CLKINb0

CLKIN0

Bank 0

CLKb0

CLK0

OEb[H:A]

2, 4, or 8 output enables

Figure 1. Simplified Block Diagram and Mux Logic

R31DS0020EU0107 Rev.1.07

July 26, 2023

Page 1

12 3 4 5 6 7...69

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