R5108G Series
Watchdog Timer Equipped with SENSE Pin with VD
The R5108G Series are CMOS-based system power ICs with a voltage detector (VD) and watchdog timer (WDT) integrated in a single chip.
R5108G monitors the power system of devices equipped with microprocessors and prevents system runaway with a reset signal when a
malfunction occurs. R5108G is equipped with the function that inhibits clock monitoring of the WDT (INH). Since R5108G has a SENSE pin
for monitoring voltage separately from the power pin, its reset signal does not become unstable as long as power supply is secured and
the "L" can be maintained.
FEATURES
• Supply Current (ISS) ························Typ. 11μA (VDD=-VDET+0.5V,
Clock pulse input)
• Operating Voltage Range (VDD) ······1.5V to 6.0V
(VD Section)
• Output Delay Time (tPLH)·················Typ. 370ms (CD=0.1μF)
<
• Output Delay Time Accuracy··········± 16% (-40°C Topt 105°C)
=
=
(WDT Section)
• Watchdog Timeout Period (tWD)······Typ. 310ms (CTW=0.1μF)
•
•
•
Detector Threshold Range (-VDET
Detector Threshold Accuracy ··········± 1%
Temp. coeff. of Detector Threshold ···Typ. ± 100ppm/°C
)
···1.5V to 5.5V (internally fixed)
• Reset Hold Time of WDT (tWR) ·······Typ. 34ms (CTW=0.1μF)
<
•
Watchdog Timeout Period Accuracy ····± 33% (-40°C Topt 105°C)
• Package ·········································SSOP-8G
=
=
°
°
°
(The above shows specification at Topt=25 C. Design assurance value at -40 C
Topt
105 C is also available. For details, please refer to the datasheet.)
=
=
BLOCK DIAGRAMS
TYPICAL APPLICATION
R5108Gxx1A
R5108Gxx1C
(Nch. open drain output)
(CMOS output)
Power Supply
Microprocessor
VDD
SENSE
SENSE
V
DD
VDD
R
8
2
6
VDD
RESETB
1
5
RESET
I/O
C
D
CD
SENSE
Vref2
Vref1
Vref2
Vref1
R5108Gxx1A
SCK
CTW
GND
SCK
GND
SCK
Series
INH
CD
C
TW
CTW
WATCHDOG
TIMER
CLOCK
DETECTOR
WATCHDOG
TIMER
CLOCK
DETECTOR
SW
3
7
GND
4
CTW
CD
RESETB
RESETB
INH
INH
SELECTION GUIDE
.
xx.
:
Specify the detector threshold within the range 1.5V (
in 0.1V steps.
.
15
.
) to 5.5V (
.
55
.
)
Package
Quantity per Reel
Part No.
SSOP-8G
3,000 pcs
R5108G
.
xx.
1.
∗-TR-F
: Select the output type from (
.
A
.
) Nch. open drain or (
.
C
.
) CMOS.
.
∗
PACKAGE (Top View)
TIMING CHART
SSOP-8G
8
7
6
5
VDD
V
INH
+VDET
-VDET
1
2
3
4
V
SENSE
1
2
RESETB Output pin for Reset "L" signal
SENSE Voltage SENSE pin of VD
t
PLH
tPLH
+VTCD
- VTCD
V
V
CD
Ext. Cap. pin for setting output
delay time of VD
3
CD
t
WD
tWDI
V
ref2H
4
5
6
GND
SCK
INH
Ground pin
Watchdog timer clock input pin
Inhibit pin
CTW
V
ref2L
t
PHL
tWR
Ext. Cap. pin for setting reset and
watchdog timeout period of WDT
Power supply pin
V
SCK
7
8
C
TW
t
PLH
VDD
V
RESETB
APPLICATION
∗tPHL : Output delay time
∗tWDI : tWD/10 (SCK pulses input during this period are ignored.)
• Monitoring of the power system of devices equipped with microprocessors
No.EK-171-091101
CMOS Microprocessor Supervisory
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