Datasheet > R1RW0408D

R1RW0408D

更新时间： 2024-02-03 03:08:30

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
14页	86K
描述
4M High Speed SRAM (512-kword x 8-bit)

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中文翻译

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数据手册

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R1RW0408D 数据手册

R1RW0408D Series

Write Cycle

R1RW0408D

-2

Parameter

Symbol Min

Max

Unit

Notes

Write cycle time

t_WC

t_AW

t_CW

t_WP

t_AS

Address valid to end of write

Chip select to end of write

Write pulse width

Address setup time

Write recovery time

t_WR

t_DW

t_DH

Data to write time overlap

Data hold from write time

Write disable to output in low-Z

Output disable to output in high-Z

Write enable to output in high-Z

t_OW

t_OHZ

t_WHZ

Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is

sampled and not 100% tested.

2. Address should be valid prior to or coincident with CS# transition low.

3. WE# and/or CS# must be high during address transition time.

4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input

signals of opposite phase to the outputs must not be applied to them.

5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#

transition, output remains a high impedance state.

6. t_ASis measured from the latest address transition to the later of CS# or WE# going low.

7. t_WRis measured from the earlier of CS# or WE# going high to the first address transition.

8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest

transition among CS# going low and WE# going low. A write ends at the earliest transition

among CS# going high and WE# going high. t_WPis measured from the beginning of write to the

end of write.

9. t_CWis measured from the later of CS# going low to the end of write.

Rev.1.00, Mar.12.2004, page 8 of 12

1...5 6 789 10 11...14

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