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QLU22108-PT280C

更新时间： 2024-02-14 02:58:52

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QLU22108-PT280C 数据手册

QLU22108-PT280C Device Data Sheet

Utopia Level 2 to 1 Multiplexer

• • • • • •

1.0 Utopia Level 2/1 Multiplexer Core Features

• Implements an Utopia L2 Slave and two to four Utopia L1 Masters providing a solution

to aggregate Utopia Level 1 Slave devices to a Level 2 Master

• Compliant with ATM-Forum af-phy-0039.000 (Level 2) and af-phy-0017.000 (Level 1)

• Implements 8-bit data busses

• Level 2 interface implements MPHY mode with direct status indication

• Round Robin port arbitration independent for Egress (TX) and Ingress (RX) data pathes

• Level 2 interface meets 50MHz performance offering up to 400Mbps cell rate transfers

• Level 1 interface meets 25MHz performance offering up to 200Mbps cell rate transfers

per Port

• Single chip solution with up to 3 east ports for improved system integration

• Supports cell level transfer mode

• Cell and clock rate decoupling with on chip FIFOs

• Up to 1 KByte of on chip FIFO per data direction

• Integrated management interface and built-in errored cell discard

• ATM Cell size programmable via external pins from 16 to 128 bytes

• Level 2 MPHY address programmable via external pins

• Optional Utopia parity generation/checking enable/disable via external pin

• Built in JTAG port (IEEE1149 compliant)

• Simulation model available for system level verification (Contact Quicklogic for details)

• Solution also available as flexible Soft-IP core, delivered with a full device modelization

and verification testbenches

•

QLU22108-PT280C Device Data Sheet

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