Datasheet > QL12X16B-2PL68C

QL12X16B-2PL68C

更新时间： 2024-11-18 23:30:39

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
8页	367K
描述
Field Programmable Gate Array (FPGA)

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QL12X16B-2PL68C 数据手册

QL12X16B

pASIC^®1 Family

Very-High-Speed CMOS FPGA

Rev C

pASIC

HIGHLIGHTS

Very High Speed – ViaLink metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density

–

A 12-by-16 array of 192 logic cells

provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and

84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.

…2,000

usable ASIC gates,

88 I/O pins

Low-Power, High-Output Drive

– Standby current typically 2

mA. A 16-bit counter operating at 100 MHz consumes less than 50

mA. Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools

–

Designs entered and

simulated using QuickLogic's new QuickWorks development

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

QL12x16B

Block Diagram

192 Logic Cells

Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-13

12 3 4 5 6 7 8

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型号	品牌	获取价格	描述	数据表
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