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Q24S30020-NS00G

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Q24S30020-NS00G 数据手册

Q24S30020 DC-DC Converter Data Sheet

18-36 VDC Input, 2.0 VDC @ 30 A Output

i_S

i_C

10 H

source

inductance

33 F

ESR <1

electrolytic

capacitor

1 F

ceramic

capacitor

Family

DC/DC

Converter



Vout

Vsource

Fig. 23: Test setup for measuring input reflected ripple cur-

rents, i_cand i_s.

Fig. 22: Output voltage ripple (20 mV/div.) at full rated load

current into a resistive load with Co = 10 F tantalum + 1uF ce-

ramic and Vin = 24 V. Time scale: 1 s/div.

Fig. 24: Input reflected ripple current, i_c(100 mA/div), meas-

ured at input terminals at full rated load current and Vin = 24 V.

Refer to Fig. 23 for test setup. Time scale: 1 s/div.

Fig. 25: Input reflected ripple current, i_s(10 mA/div), measured

through 10 H at the source at full rated load current and Vin =

24 V. Refer to Fig. 23 for test setup. Time scale: 1s/div.

MCD10218 Rev. 1.0, 23-Aug-10

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