TPS659110, TPS659112, TPS659113
www.ti.com
SWCS067A –AUGUST 2011–REVISED OCTOBER 2011
Power Management Unit with DCDC Controller
Check for Samples: TPS659110, TPS659112, TPS659113
1
FEATURES
power initialization reset (PWRDN) for thermal
reset input
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The purpose of the TPS659110 device is to
provide the following resources:
•
32-kHz clock and reset (NRESPWRON) for
system and an additional output for reset
signal
•
•
•
Embedded power controller (EPC) with
EEPROM programmability
•
•
Watchdog
Two efficient step-down DCDC converters for
processor cores (VDD1, VDD2)
Two ON/OFF LED pulse generators and one
PWM generator
One efficient step-down DCDC converter for
I/O power (VIO)
•
•
Two comparators for system control,
connected to VCCS pin
A JTAG® and boundary scan, but not
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•
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One controller for external FETs (VDDCtrl)
Dynamic voltage scaling for processor cores
accessible in functional mode (test purpose)
Eight LDO voltage regulators and one RTC
LDO (supply for internal RTC)
APPLICATIONS
•
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One high-speed I2C interface for
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Portable and handheld systems
general-purpose control commands (CTL-I2C)
Two independent enable signals for
controlling power resources (EN1, EN2).
Alternatively, these pins can be used as a
high-speed I2C interface dedicated for voltage
scaling for VDD1 and VDD2.
DESCRIPTION
The TPS659110 is an integrated Power Management
IC available in 98-pin 0.65-mm pitch BGA package
and dedicated to applications powered by one Li-Ion
or Li-Ion polymer battery cell or 3-series Ni-MH cells
or a 5 V input, and which require multiple power rails.
The device provides three step-down converters, one
controller for external FETs to support high current
rail, eight LDOs, and is designed to be flexible PMIC
for supporting different processors and applications.
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Thermal shutdown protection and hot-die
detection
A real-time clock (RTC) resource with:
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Oscillator for 32.768-kHz crystal or 32-kHz
built-in RC oscillator
Two of the step-down converters provide power for
dual processor cores and support dynamic voltage
scaling by a dedicated I2C interface for optimum
power savings. The third converter provides power for
the I/Os and memory in the system.
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–
Date, time and calendar
Alarm capability
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Nine configurable GPIOs with multiplexed
feature support:
The device includes eight general-purpose LDOs
providing a wide range of voltage and current
capabilities. Five of the LDOs support 1.0 to 3.3 V
with 100-mV step and three (LDO1, LDO2, LDO4)
support 1.0 to 3.3 V with 50-mV step. All LDOs are
fully controllable by the I2C interface.
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Four can be used as enable for external
resources, included into power up
sequence and controlled by state-machine.
–
As GPI, GPIOs support logic-level detection
and can generate maskable interrupt for
wake-up.
In addition to the power resources, the device
contains an EPC to manage the power sequencing
requirements of systems and an RTC. Power
sequencing is programmable by EEPROM.
–
–
Two of the GPIOs have 10 mA current sink
capability for driving LEDs.
DCDCs switching synchronization through
an external 3-MHz clock.
Figure 1 shows the top-level diagram of the device.
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Two reset inputs, for cold reset (HDRST) and a
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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JTAG is a registered trademark of JTAG Technologies, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
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